JPH0242243B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clamp circuit, and more particularly to a clamp at an output point that extracts a composite output of constant current outputs.

Conventionally, a diode limiter is installed in the clamp of an output circuit that performs current synthesis at the output point.
In such a clamp circuit, since the current at the output point is passed to the outside and clamped, it has drawbacks such as current loss and fluctuations in the output level point.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an output clamp circuit that saves current, stabilizes operation, and improves clamp operation speed.

That is, the output clamp circuit of the present invention includes an output circuit 2 in which a second transistor 8 that sinks a constant current output is connected to a first transistor 6 that outputs a constant current output, and the first and second transistors a third transistor constituting a current inverting circuit with the second transistor.
A transistor 20 is installed between the output point and the base of the second transistor, and a fourth transistor 26 to which the operating current is supplied by the third transistor is installed between the output point and the base of the second transistor.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.

FIG. 1 shows an embodiment of the output clamp circuit of the present invention. In FIG. 1, an amplifier circuit 4 such as a differential amplifier that generates a differential current output is installed at the front stage of an output circuit 2, and is provided with a current output generated by amplifying a signal S or the like.

A first transistor 6 and a second transistor 8 are installed in the output section of the output circuit 2, and these transistors 6 and 8 are connected to a positive potential line on which a power supply terminal 10 is formed and a common terminal 12. It is connected to a common line installed at
A connection point between the collectors of each transistor 6 and 8 is set to an output point of the output circuit 2, and an output terminal 14 is formed.

The transistor 6 is on the side that outputs a constant current output, and a transistor 16 configured as a diode with a common base and collector is connected between its base and emitter.
The base and collector of the transistor 6 and the base of the transistor 6 are connected to one output point 18A of the amplifier circuit 4. That is, the transistors 6 and 16 constitute a current inversion circuit, and the current flowing to the output point 18A is inverted and flows to the transistor 6.

Further, the transistor 8 is set to the side that sinks a constant current output, and a transistor 20 configured as a diode with a common base and collector is connected between its base and emitter, and the transistors 8 and 20 constitute a current inverting circuit. are doing.

A transistor 22 is connected between the base and collector of the transistor 20 and the positive potential line with its emitter on the positive potential side, and a transistor with a common base and collector is connected between the base and emitter of the transistor 22. 24 is connected, and the transistors 22 and 24 constitute a current inversion circuit. That is, the current flowing to the output point 18B is
It is inverted at 0 and 8 and flows to transistor 8.

The emitter and collector of a transistor 26 are connected between the output point formed at the collectors of the transistors 6 and 8 and the common base of the transistors 8 and 20, and the base is connected to the base and collector of the transistor 20. are commonly connected.

The operation will be explained based on the above configuration.

Assuming that the base-emitter voltages of the transistors 20 and 26 are V _BE1 and V _BE2 (or V _BE1 = V _BE2 = V _BE ), the clamp potential V _L of the output terminal 14 is V _L = V _BE1 + V _BE2 = 2V _BE ...(1) becomes.

That is, if the current flowing from transistor 6 is I ₁ and the current sucked into transistor 8 is I ₂ , then when the output level rises and is clamped, I ₁ > I ₂
becomes. Therefore, the difference current ΔI flows out from the _{output point} , and the output level increases by that amount.

In this case, the output level is the clamp potential V _L
When the difference current ΔI exceeds ΔI, the clamp circuit composed of the transistors 20 and 26 has a low impedance, so the difference current ΔI passes through the transistor 26 and flows into the bases of the transistor 20 and the transistor 8. As a result, the drawing ability of the transistor 8 increases, the current ΔI is absorbed, and the output level is immediately clamped to the clamp voltage V _L.

According to such a configuration, since the current output is absorbed inside the output circuit 2 without flowing out to the outside,
Clamping operation is stabilized, current can be saved, and clamping speed is improved.

FIGS. 2 and 3 show another embodiment of the output clamp circuit of the present invention, in which the same parts as in the previous embodiment are given the same reference numerals.

In the embodiment shown in FIG. 2, the base and collector of the transistor 28 are
The emitters are connected, the bases of transistors 28 and 26 are shared, and the collector of transistor 26 is connected to the bases of transistors 20 and 8. The clamp potential V _L in this embodiment is the sum of the base-emitter voltages of each transistor 20, 26, and 28. For example, if the base-emitter voltages (V _BE ) of each transistor are the same, the value is
It becomes 3V _BE .

In the embodiment shown in FIG. 3, a variable voltage source 30 is installed between the base of the transistor 26, the base/collector of the transistor 20, and the base of the transistor 8. In this way, if the voltage set by the variable voltage source 30 is V ₃₀ , the clamp potential V _L will be V _L = V _BE1 + V _BE2 + V ₃₀ ≒ 2V _BE + V ₃₀ (3), and the variable voltage An arbitrary clamping potential can be set at the source 30.

In the embodiment, the amplifier circuit 4 is installed at the front stage, but the present invention is not limited to the case where such an amplifier circuit is installed, and can be used for various current output circuits.

As explained above, according to the present invention, the current is increased or decreased within the output without flowing out to the outside, and the current is transferred to the clamp potential, which stabilizes the potential and improves the clamp operation speed. , current savings can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the output clamp circuit of the invention, and FIGS. 2 and 3 are circuit diagrams showing other embodiments of the output clamp circuit of the invention. 2... Output circuit, 6... First transistor,
8... second transistor, 20... third transistor, 26... fourth transistor, 30...
...variable voltage source.

Claims (1)

[Claims] 1. An output circuit is installed in which a second transistor that sinks a constant current output is connected to a first transistor that outputs a constant current output, and the connection point between the first and second transistors is an output point. and a third transistor constituting a current inverting circuit with the second transistor, and an operating current is applied by the third transistor between the output point and the base of the second transistor. An output clamp circuit characterized in that a fourth transistor is installed. 2. The output clamp circuit according to claim 1, wherein the third transistor has its base and collector connected in common and functions as a diode. 3. The output clamp circuit according to claim 2, wherein a variable voltage source is installed between the base of the fourth transistor and the base/collector of the third transistor.