JPH0242744A - Sorting of chip - Google Patents

Sorting of chip

Info

Publication number
JPH0242744A
JPH0242744A JP63193840A JP19384088A JPH0242744A JP H0242744 A JPH0242744 A JP H0242744A JP 63193840 A JP63193840 A JP 63193840A JP 19384088 A JP19384088 A JP 19384088A JP H0242744 A JPH0242744 A JP H0242744A
Authority
JP
Japan
Prior art keywords
wafer
sheet
chip
medium layer
scribed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63193840A
Other languages
Japanese (ja)
Inventor
Yasuo Fujima
藤間 保雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63193840A priority Critical patent/JPH0242744A/en
Publication of JPH0242744A publication Critical patent/JPH0242744A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Electric Properties And Detecting Electric Faults (AREA)
  • Sorting Of Articles (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To shorten a sorting time by installing the following: a sheet-pasting process; a characteristic-measuring process of individual elements; a store and classification process of a measured result; a scribing process of a wafer; a wafer-breaking process; a sheet-stretching process; die-mounting process. CONSTITUTION:A wafer is pasted onto the surface of a sheet where an adhesive layer has been formed on its surface and a magnetic medium layer has been formed on its rear; individual characteristics of individual elements inside the wafer are measured by using a prober or the like. A measured result is stored in the magnetic medium layer situated on the rear of the individual elements; the wafer is scribed. The scribed wafer is broken; a sheet is stretched; spaces are formed in broken parts of the wafer. A good chip is discriminated on the basis of magnetic information; it is mounted in a prescribed position of a package. Thereby, it is possible to eliminate a drawback that a sorting time becomes long by a visual inspection of a human being.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はチップ選別方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a chip sorting method.

〔従来の技術〕[Conventional technology]

次に従来のチップ選別方法について図面を参照して詳細
に説明する。
Next, a conventional chip sorting method will be explained in detail with reference to the drawings.

第2図は従来のチップ選別方法の一例を示すフローチャ
ートである。
FIG. 2 is a flowchart showing an example of a conventional chip sorting method.

第2図に示すチップ選別方法は、 (A)拡散、ホトエツチング等の工程を経たウェハ内の
素子の各特性をプローバ等で個々に測定する測定工程(
Sll)、 (B)不良素子にスクラッチマーキング(またはインク
マーキング、磁性インクマーキング)をつけて良否を分
類する分類工程(S12)、(C)ウェハをスクライビ
ングするスクライビング工程(S13)、 (D)ウェハを粘着剤を片面に有するプ°ラスチック製
のシートに張付ける張付工程(S14)、(E)ウェハ
をチップ化するブレーキング工程(S15)、 (F)シートを拡張し前記ウェハのブレーキング部分に
間隔を設けるシート拡張工程(S16)、(G)良品チ
ップを判別してパッケージの所定の位置に搭載するダイ
マウント工程(S17)、とを含んで構成される。
The chip sorting method shown in Fig. 2 consists of (A) a measurement step in which each characteristic of the elements in the wafer, which has gone through processes such as diffusion and photoetching, is measured individually using a prober, etc.;
Sll), (B) A classification step (S12) in which defective elements are marked with scratch marks (or ink markings, magnetic ink markings) and classified as good or bad (C) A scribing step (S13) in which wafers are scribed, (D) Wafers (S14); (E) A breaking step (S15) for converting the wafer into chips; (F) Expanding the sheet and breaking the wafer. The process includes the following steps: a sheet expansion step (S16) for providing intervals between portions, and (G) a die mounting step (S17) for identifying non-defective chips and mounting them at predetermined positions on the package.

第3図は第2図に示すブレーキング工程S15終了後の
チップの形状を示す断面図である。
FIG. 3 is a sectional view showing the shape of the chip after the braking step S15 shown in FIG. 2 is completed.

シート20に張付いているチップ31〜34は、シリコ
ン結晶の性質上、ある角度を持ってブレーキングされる
ので、真上に持上げてダイマウントできない。そこでチ
ップ31〜34に間隔を設は真上に持上げてダイマウン
トできるようにするため、シート20を拡張するシート
拡張工程S16が必要になる。
Because the chips 31 to 34 stuck to the sheet 20 are braked at a certain angle due to the nature of silicon crystal, they cannot be lifted directly upward and die-mounted. Therefore, a sheet expansion step S16 is required to expand the sheet 20 in order to set a space between the chips 31 to 34 and lift them directly above to enable die mounting.

シート拡張工程S16を実施すると各チップの相対位置
は不定になるため、ダイマウント工程S17ではマウン
トせんとするチップの位置をを画像認識装置を用いて調
べなければならない。
When the sheet expansion step S16 is performed, the relative position of each chip becomes indefinite, so in the die mounting step S17, the position of the chip to be mounted must be checked using an image recognition device.

画像認識装置は搭載せんとするチップの良否をも調べ、
良品チップのみをマウントするために利用されるが、認
識率が低い場合はダイマウント工程S17以前に、不良
チップを人間が目視で排除しておかなけれはならない。
The image recognition device also checks the quality of the chip to be installed.
It is used to mount only good chips, but if the recognition rate is low, a human must visually remove defective chips before the die mounting step S17.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のチップ選別方法は、ダイマウント工程前
に良品チップとその位置を機械的に移動する光学系を用
いて調べ、不良チップ認識率が低い場合は人間が目視で
排除しておかなけれはならないので、選別時間が長くな
るという欠点があった。
The conventional chip sorting method described above uses an optical system that mechanically moves the good chips and their positions before the die mounting process, and if the recognition rate of bad chips is low, they must be visually removed by humans. Therefore, there was a drawback that the sorting time was increased.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のチップ選別方法は、 (A)表面に粘着剤層を、裏面に磁性媒体層を有するシ
ートの前記表面にウェハを張付けるシート張付工程、 (B)前記ウェハ内の各素子の各特性をプローバ等で個
々に測定する測定工程 (C)前記各素子の裏面に位置する前記磁性媒体層に前
記測定結果を記憶させる分類工程、(D)前記ウェハを
スクライビングするスクライビング工程、 (R)スクライビングされたウェハをブレーキングする
ブレーキング工程、 (F)前記シートを拡張し前記ウェハのブレーキング部
分に間隔を設けるシート拡張工程、(G)前記磁気情報
にもとづいて良品チップを判別してパッケージの所定の
位置に搭載するダイマウント工程、 とを含んで構成される。
The chip sorting method of the present invention includes: (A) a sheet pasting step of pasting a wafer on the front surface of a sheet having an adhesive layer on the front surface and a magnetic medium layer on the back surface; (B) each of the elements in the wafer; (C) A classification step of storing the measurement results in the magnetic medium layer located on the back surface of each element; (D) A scribing step of scribing the wafer; (R) a braking step of braking the scribed wafer; (F) a sheet expansion step of expanding the sheet to provide a gap between the braking portions of the wafer; and (G) determining non-defective chips based on the magnetic information and packaging them. and a die mounting process for mounting the device at a predetermined position.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例を示すフローチャートである
FIG. 1 is a flowchart showing one embodiment of the present invention.

工程S1 表面に粘着剤層を、裏面に磁性媒体層を有するシートの
前記表面にウェハを張付ける。
Step S1: A wafer is attached to the front surface of a sheet having an adhesive layer on the front surface and a magnetic medium layer on the back surface.

工程S2 前記ウェハ内の各素子の各特性をプローバ等で個々に測
定する。
Step S2: Each characteristic of each element within the wafer is individually measured using a prober or the like.

工程S3 前記各素子の裏面に位置する前記磁性媒体層に前記測定
結果を記憶させる。
Step S3: Storing the measurement results in the magnetic medium layer located on the back surface of each element.

工程S4 前記ウェハをスクライビングする。Process S4 The wafer is scribed.

工程S5 スクライビングされたウェハをブレーキングする。Process S5 Braking the scribed wafer.

工程S6 前記シートを拡張し前記ウェハのブレーキング部分に間
隔を設ける。
Step S6: Expanding the sheet to provide a spacing between the braking portions of the wafer.

工程S7 前記磁気情報にもとづいて良品チップを判別してパッケ
ージの所定の位置に搭載する。
Step S7: A non-defective chip is determined based on the magnetic information and mounted at a predetermined position on the package.

工程S6において、シートはウェハのブレーキング部分
が主として拡張され、チップに粘着している部分のシー
トはチップに保護されて殆んど拡張しないから、磁気情
報は破壊されない。
In step S6, the sheet is expanded mainly at the breaking part of the wafer, and the sheet in the area adhering to the chip is protected by the chip and hardly expands, so the magnetic information is not destroyed.

〔発明の効果〕〔Effect of the invention〕

本発明のチップ選別方法は、選別時間が短縮できるとい
う効果がある。
The chip sorting method of the present invention has the effect of shortening the sorting time.

勇7Isamu 7

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すフローチャート、第2
図は従来の一例を示すフローチャート、第3図は第2図
に示すブレーキング工程終了後のチップの形状を示す断
面図である。 20・・・・・・シート、31〜34・・・・・・チッ
プ。 代理人 弁理士  内 原  晋
FIG. 1 is a flowchart showing one embodiment of the present invention, and FIG.
The figure is a flowchart showing an example of the conventional method, and FIG. 3 is a sectional view showing the shape of the chip after the braking process shown in FIG. 2 is completed. 20... Sheet, 31-34... Chip. Agent Patent Attorney Susumu Uchihara

Claims (1)

【特許請求の範囲】 (A)表面に粘着剤層を、裏面に磁性媒体層を有するシ
ートの前記表面にウェハを張付けるシート張付工程、 (B)前記ウェハ内の各素子の各特性をプローバ等で個
々に測定する測定工程 (C)前記各素子の裏面に位置する前記磁性媒体層に前
記測定結果を磁気情報として記憶させる分類工程、 (D)前記ウェハをスクライビングするスクライビング
工程、 (E)スクライビングされたウェハをブレーキングする
ブレーキング工程、 (F)前記シートを拡張し前記ウェハのブレーキング部
分に間隔を設けるシート拡張工程、 (G)前記磁気情報にもとづいて良品チップを判別して
パッケージの所定の位置に搭載するダイマウント工程、 とを含むことを特徴とするチップ選別方法。
[Claims] (A) A sheet pasting step of pasting a wafer on the surface of a sheet having an adhesive layer on the front surface and a magnetic medium layer on the back surface; (B) Characteristics of each element in the wafer. (C) A classification step of storing the measurement results as magnetic information in the magnetic medium layer located on the back surface of each element; (D) A scribing step of scribing the wafer; (E) ) a braking step of braking the scribed wafer; (F) a sheet expansion step of expanding the sheet to provide a gap between the braking portions of the wafer; (G) determining non-defective chips based on the magnetic information. A die-mounting step of mounting the chip in a predetermined position of the package.
JP63193840A 1988-08-02 1988-08-02 Sorting of chip Pending JPH0242744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63193840A JPH0242744A (en) 1988-08-02 1988-08-02 Sorting of chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63193840A JPH0242744A (en) 1988-08-02 1988-08-02 Sorting of chip

Publications (1)

Publication Number Publication Date
JPH0242744A true JPH0242744A (en) 1990-02-13

Family

ID=16314612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63193840A Pending JPH0242744A (en) 1988-08-02 1988-08-02 Sorting of chip

Country Status (1)

Country Link
JP (1) JPH0242744A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04174529A (en) * 1990-11-07 1992-06-22 Nec Corp Wafer marking equipment
CN116809429A (en) * 2023-07-12 2023-09-29 无锡奥特维科技股份有限公司 Silicon wafer receiving device and silicon wafer sorting system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04174529A (en) * 1990-11-07 1992-06-22 Nec Corp Wafer marking equipment
CN116809429A (en) * 2023-07-12 2023-09-29 无锡奥特维科技股份有限公司 Silicon wafer receiving device and silicon wafer sorting system

Similar Documents

Publication Publication Date Title
US4641353A (en) Inspection method and apparatus for a mask pattern used in semiconductor device fabrication
US5827394A (en) Step and repeat exposure method for loosening integrated circuit dice from a radiation sensitive adhesive tape backing
EP1484791A4 (en) DIE CUTTING METHOD, INTEGRATED CIRCUIT ELEMENT INSPECTION METHOD, SUBSTRATE SUPPORT DEVICE, AND SELF-ADHESIVE FILM
US6391679B1 (en) Method of processing a single semiconductor using at least one carrier element
KR970023935A (en) Process bonding inspection method of semiconductor device
JPH0242744A (en) Sorting of chip
KR950014897A (en) Chip holding device for burn-in test and manufacturing method thereof
US20070017630A1 (en) Methods for releasably attaching support members to microfeature workpieces and microfeature assemblies formed using such methods
US20240227316A9 (en) Bonding apparatus, bonding method and article manufacturing method
JPH05299484A (en) Semiconductor wafer
JPH0425040A (en) Manufacture of semiconductor device
JPH02299216A (en) Semiconductor device
JPH03228345A (en) Semiconductor chip and inspection of the chip
JPS5966112A (en) Semiconductor chip
JP2969822B2 (en) Semiconductor device manufacturing management system
JPH01125949A (en) Dicing device for wafer
KR970030526A (en) Manufacturing method of semiconductor chip package using support ring to prevent lead damage
JPH0287540A (en) Inspection of semiconductor wafer
KR20060021063A (en) Wafers for Effective Electrical Property Testing
JPS63276240A (en) Manufacture of semiconductor device
JPH07106390A (en) Semiconductor substrate
JPS6185837A (en) Chip separating device
KR950002014A (en) Semiconductor device, manufacturing method and alignment method
JPS5818780B2 (en) How to detect semiconductor pellets
JPH11233793A (en) Method for manufacturing semiconductor device