JPH0242745A - Large-scale integrated circuit - Google Patents

Abstract

PURPOSE:To revise a logic circuit simply and in a short time by a method wherein, when a logic function is changed, a standard cell as an object to changed and a dummy standard cell are wired and connected. CONSTITUTION:In addition to a standard cell group 2 composed of a plurality of standard cells formed on a semiconductor chip 1 used to a realize a specific logic function, a dummy standard cell group 3 composed of a plurality of standard cells having a specific logic circuit is formed in a blank region on the semiconductor chip 1. When the specific logic function realized by using the standard cell group 2 is revised and changed, the dummy standard cell group 3 is used; a standard cell as an object to be revised and a dummy standard cell are wired; the logic function is revised. Thereby, a revision can be executed simply, efficiently and in a short time.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention connects standard cells of a group of standard cells formed on a semiconductor chip with wires to realize a specific logic function. Concerning large-scale integrated circuits.

(Prior Art) Recently, the development of integrated circuit technology has been remarkable, and gate array technology that can realize large integrated circuits in a short period of time is attracting attention. This gate array is formed by laying basic cell tiles, which are the smallest unit of logic gates, on a semiconductor chip, and by wiring these basic cell tiles, various logic gates are realized. A specific logic circuit is realized by wiring between gates.

In contrast, recently, large-scale integrated circuits with a standard cell structure have been developed for the purpose of even larger circuit integration. Large-scale integrated circuits with this standard cell structure are constructed by forming multiple logic gates as standard cells on a semiconductor chip in advance, and by wiring these standard cells (logic gates) to create a specific logic circuit. This is to realize the following. A large-scale integrated circuit having such a standard cell structure has a feature that the degree of integration can be significantly increased compared to the above-mentioned large-scale integrated circuit using a gate array.

However, when it becomes necessary to modify (refine) a part of a specific logic circuit realized by wiring between standard Φ cells, the following problems occur.

That is, in the case of a large-scale integrated circuit using the gate array described above, it is possible to modify the logic function by simply modifying the mask of the wiring layer connecting the basic Φ cell tiles in the same way as in the mask design process. In a large-scale integrated circuit with a standard cell structure, it becomes necessary to modify all the masks of the cell part and the wiring part. As a result, it is undeniable that modifying the logic function requires a period of time comparable to that required for designing the circuit, and that the amount of work required is extremely large.

(Problem to be solved by the invention) As described above, in large-scale integrated circuits with a conventional standard cell structure, it is very difficult to modify the logical functions implemented therein, and it is difficult to modify them quickly. There were problems that could not be addressed.

The present invention has been made in consideration of these circumstances, and its purpose is to provide a large-scale integration of a structure in which modifications to logic circuits realized using standard cells can be easily and quickly made. The purpose is to provide circuits.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a large-scale integrated circuit that connects standard cells of a group of standard cells formed on a semiconductor chip with wires to realize a specific logic function. In particular, a dummy standard cell group is formed in advance on the semiconductor chip on which the standard cell group is formed, separate from the standard cell group, and a logical function is realized using the standard cell group. When changing φ, use the dummy standard cell group mentioned above, and select the standard cell to be changed and the dummy standard φ.
This feature is characterized in that the above-mentioned modification of the logic function can be handled by wiring connection to the cells.

In other words, the present invention is characterized in that it is possible to cope with the modification of the logic function simply by modifying the mask of the wiring section that connects the standard cells and realizes the predetermined logic function.

(Function) According to the present invention, by effectively using the dummy standard cell group formed in advance on the semiconductor chip on which the standard cell group is formed, the mask of the cell part that realizes the standard cell group is masked. The logic function can be modified only by modifying the mask of the wiring portion without modification. As a result, it becomes possible to modify the logic function realized using the standard cell group easily, efficiently, and in a short time.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

The large-scale integrated circuit according to the present invention is characterized by a standard cell group consisting of a plurality of standard cells formed on a semiconductor chip l to realize a specific logical function, as shown in FIG. In addition to 2, a dummy first standard cell group 3 consisting of a plurality of standard ψ cells realizing a predetermined logic circuit is formed in the vacant area on the semiconductor chip l, and the standard cell group 2 is used to form a dummy first standard cell group 3. When modifying or modifying a specific logic function realized by It is characterized by the fact that it is made to obtain.

Note that the dummy standard cell group 3 may be realized as a collection of unused standard cells in the standard or cell group 2. The standard cells in this dummy standard cell group 3 usually have their input ends wired to ground, and the input level is set to “0”.
By fixing it to ``, the power consumption due to switching operation is set to be minimized.

In FIG. 1, specific logic functions using standard cell group 2 include NAND game) 11.
N Kano Gate 12. Series circuit of AND gate 13.

It is realized as a logic function circuit including a NAND gate 14 and a NAND gate 14 in parallel thereto. Also, as dummy standard cell group 3, there are two inverting circuits 21, 22 and AN
D gate 23 is prepared.

A large-scale integrated circuit with such a configuration is designed by designing masks for each cell part of standard cell group 2 and dummy standard cell group 3, and further interconnecting the standard cells in cell groups 2 and 3. This is achieved by designing a mask for a wiring section that implements a predetermined logical function.

However, although a large-scale integrated circuit that realizes a predetermined logic function has been designed in this way, for example, the logic function of the circuit function portion 5 shown by the broken line in FIG. 1 is changed as shown in FIG. 2. If necessary, the wiring pattern of the large-scale integrated circuit according to this embodiment can be changed as shown in FIG. 3 using the standard cells 21, 22, and 23 of the dummy standard cell group 3. This is to deal with the modification of the above logical function. Modification of this logical function is realized by changing and modifying the mask of the wiring section described above.

That is, by connecting the inverting circuit 21 to the output stage of the NAND gate 11, the logical function is changed to AND, and by similarly connecting the inverting circuit 22 to the output stage of the NOA gate 12, the logical function is changed to OR. Changes and corrections have been made. And regarding modification of the circuit function of AND gate 13, AN
I) By using the gate 23 to additionally input the output of the NAND gate 14, the function can be modified.

According to the embodiment circuit configured so that the logic function can be modified using such dummy standard cell group 3, it is possible to simply modify the mask of the cell portion of standard cell group 2, etc. By simply modifying the mask of the wiring section for connecting cells, the logical function can be easily modified.

As a result, compared to conventional large-scale integrated circuits with a standard cell structure, when modifying the logic function, there is no need to modify the mask of the cell section, so the period required for modification can be significantly shortened. It becomes possible. Further, the mask correction of the wiring part can be carried out manually, for example, and it is possible to carry out the correction simply and in a short time.

Therefore, the processing load required for modifying the logic function can be greatly reduced, and it becomes possible to modify the logic function in a large-scale integrated circuit having a standard cell structure at low cost and in a short period of time.

Note that the present invention is not limited to the embodiments described above. Although the explanation here uses an example of a large-scale integrated circuit that has only standard cells, the same applies to the case of realizing a super-integrated circuit that combines a general-purpose microprocessor or peripheral peripheral LSI mask with a standard cell circuit. It is possible to apply it to Further, the number of cells to be prepared as dummy cells and their logical functions may be determined in accordance with the circuit specifications. In addition, the present invention can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As explained above, according to the present invention, the logic function of a large-scale integrated circuit realized as a standard cell structure can be easily modified at low cost and in a short period of time. This has great practical effects, such as being able to significantly reduce the burden of correction processing.

[Brief explanation of the drawing]

FIG. 1 is a diagram schematically showing the configuration of a large-scale integrated circuit with a standard cell structure according to an embodiment of the present invention, and FIG. 2 is a diagram showing a modified logic function for the logic function of the circuit shown in FIG. 1. , FIG. 3 is a diagram schematically showing a modification of the logic function using a dummy standard cell group. ■...Large-scale integrated circuit, 2...Standard cell group, 3...Dummy standard cell group, 5...
Functional circuit part to be modified.

Claims (1)

[Claims] In a large-scale integrated circuit in which standard cells of a group of standard cells formed on a semiconductor chip are interconnected to realize a specific logic function, the standard cell group formed on a semiconductor chip is
A dummy standard cell group is formed separately from the cell group, and when changing the logic function realized using the standard cell group, wiring is required between the standard cell to be changed and the dummy standard cell. A large-scale integrated circuit characterized by comprising means for connecting.