JPH0242820A - A/d converter - Google Patents

Abstract

PURPOSE:To obtain the A/D converting device of satisfactory input and output linearity by using two A/D converters and canceling non-linearity such as jump or saturation, etc. CONSTITUTION:When an analog voltage to be inputted to a first A/D converter 2a is -V, an output 8 goes to be all 0. When an analog voltage to be inputted to a second A/D converter 2b is +V, the output goes to be all 1. In this condition, voltages to be impressed to terminals VH and VL of the A/D converters 2a and 2b are respectively defined as V- V, -V, +V and -V+ V. The V is the high order bit one bit corresponding part of digital data in respective elements. The output data 8 from the element 2a and output data 11 from a second digital adder 4 are added by a first digital adder 3. The average of an added value is obtained and output data can be obtained in a final digital output 12. Then, the final digital output can be obtained to cancel the non- linearity such as the jump or saturation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to high-speed A/D converters (elements), and in particular to improving the linearity thereof.

[Conventional technology]

FIG. 4 is a block diagram showing conventional A/D converters (elements) commonly commercially available, including (b) tIiAβ conversion element, (
1) Fi analog input, C5) is the clock input for A/D conversion, (6) is the reference voltage on the low potential side, (7) is the reference voltage on the high potential side, and C5 is the digitized output.

Next, the operation of this conventional example will be explained. FIG. 5 is a diagram showing the operating range of this A/D conversion element a'h. For example, when a voltage of -V is input to the analog input (1), all IQI is obtained as a digitized output signal. +V
This shows that when a voltage of The digital data to be output is n-bit, and various types are commercially available depending on the specifications of the device.

Also, the output data is usually shown in pure binary for simplicity, but other formats are also available.

Here, for simplicity, we will consider pure binary.

Next, FIG. 6 is a principle diagram showing the internal structure of the A/D conversion element αη, and shows an example of a 6-bit A/D converter.

In the figure, ag is an analog input, ■ is a conversion unit that first quantizes the upper 3 bits, and (2) is a digital data output of the upper 3 bits. ■ is the D/A converter that converts this upper bit data back into an analog value. This is a 3-bit A/D conversion section. @ indicates data output of the lower 3 bits. This type of L0 converter is called a series-parallel type A/D converter.

In this format, it is necessary that the A/D converter for the upper 3 bits and the D/A converter for the lower 3 bits are exactly the same, but in a high-speed type, this sameness is not possible. Since it is incomplete, the characteristics of the obtained 6-bit digital data are often as shown in FIG. 3 (to). That is, the digital output value corresponding to the analog input voltage jumps, decreases, and saturates every time the upper bit changes, which is repeated periodically. This is shown in Fig. 3 (13a) and (13b).

[Problems that the invention aims to solve]

Conventional A/D converters exhibit such characteristics, so 1
There was a problem in that it was difficult to obtain sufficiently good input/output linearity with a single element.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain an A/D conversion device with good input/output ag performance.

[Ninth means to solve the problem]

The A/D conversion device according to the present invention uses two A/D converters and is configured to cancel such nonlinearities such as jumps and saturation.

[Effect]

2. A/D converter t of the present invention has non-linearity in characteristics, but has the same characteristics including this non-linearity.
Using two A/D converters, only one of the reference voltage or analog input voltage to both is shifted between the A/D converters by an amount equivalent to one upper bit, and the digital output of one of the two A/D f converters is By adding the value of the upper focus bit to the digital output of the other A/D converter, the nonlinearity is canceled out, resulting in A/D conversion with good linearity. A device is obtained.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In Figure ICB, it) is an analog input, (2a).

(2b) is the same convex pole and exhibits the same characteristics including imperfections. Second A/D converter (element), +3)
, (4) is the first. 2nd digital adder, (5) is clock input, (6) is low potential side reference voltage, (1) is high potential side reference voltage, (83, (93 are first and second respectively)
The digitized output data of the A/D converters (2a) and (2b), the αa4 constant, is a value equivalent to one upper bit of the digital output data (18 in the example in Figure 6).
A description will be given of the 0th-order operation where # is a constant), (b) is the output data of the second digital adder (4), and @ is the final digital output of the present A/D converter. Figure 2 shows the first and second A/D converters (2a) and (2b) +7)
Indicates the voltage applied to VH and VL.
vH large input of D converter (2a), upper right of the figure (V-ΔV
), vL input is lower right of the figure (2)-V, 2nd OA/Di
Converter (z) The OVH input is V at the upper left of the figure, and the VL large input is at the lower left of the figure (-V+ΔV).

Therefore, when the analog input voltage input to the first A/D converter (2a) is 1, the output (8) ri all IQ
When the analog input voltage input to the second A/D converter (2b) is V, the output becomes all #II. The value ΔV is equivalent to one upper bit of the digital data output of each element.

Figure 3 shows the data of each part of the 11th part, and Q3
is the output data (9) from the second A/D converter (2b)
α4 shows the relationship between the output data (8) from the first A/D f converter (2a) and the analog input (1,). 0 Here, Wll and the second A/D converter (2a), (2b
) is shown at which jump in (13a), (13b) 7. Now, in the output data (9), one high-order bit, that is, #8' in the example of Fig. 3, is added to the second
When added by the digital adder (4), the output data (B) is shown by the broken line in Figure 3 (G).
It is clear that we get Therefore, if the output data (8) from the first A/D conversion element (2a) shown in Fig. 1 and the data (b) are added by the digital adder (3) of Kintetsu 1, and the average is taken, the The output data indicated by the thick solid line αO in FIG. 3 is obtained at the final digital output @ point of this embodiment due to the first factor. As is clear from the output data (6), (13a) and (13b)
There are no jumps, and a uniform digital output step is obtained at all input voltage points.

FIG. 7 shows another embodiment of the invention. In this figure, the same symbols as in FIG. 1 are used to indicate the same things, and 2 and @ are an analog adder provided at the input of the first A/D converter (2a). In this embodiment, a voltage ΔV corresponding to the upper 1 bit is added to the analog human power [1] in advance to the analog human power Vin of the first A/D converter (2a), and both A/D converters Vessel (2a)
, (2b) differs from the embodiment in FIG. 1 in that the reference potential is shared, but the same effect as in FIG. 3 is achieved.

〔Effect of the invention〕

As described above, if this invention is implemented, an A/D conversion device with good linearity can be obtained by simply using two general A/D conversion elements that exhibit the same characteristics, although they are imperfect. effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is a diagram showing the reference potential and operating range of both A/D converters in this embodiment, and FIG.
Figure 4 illustrating the characteristics of the /D converter and the operation of the embodiment.
The figure is a block diagram showing the configuration of a conventional A/D converter consisting of one element, FIG. 5 is a third diagram explaining the operating range of this A/D converter, and FIG. A principle diagram showing the internal structure of the converter, and FIG. 7 is a block diagram showing the structure of another embodiment of the present invention. In the figure, (1) is the analog input & (2a) is the first A/D converter, (2b) is the second A/D converter, (
3) is the first digital adder, (4) is the second digital adder, (6) is the low potential side reference potential, (7) is the high potential side reference potential, (8) is the first A/ I) Digital output data of the converter, (9) is the digital output data of the second A/D f converter, αG is a constant, (B) is the output data of the second digital adder, (6) is this This is the final digital output of the A/D converter. 2. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In a series-parallel A/D converter that performs A/D conversion by dividing upper bits and lower bits, first and second
Using an A/D converter, only one of the reference voltage or analog input voltage to the two A/D converters is shifted between the two A/D converters by an amount equivalent to one upper bit, and , By adding one bit of the upper bit to the digital output of one of the two higher-order A/D converters to the digital output of the other A/D converter, the overall A/D conversion can be calculated. An A/D conversion device characterized by improved linearity.