JPH0243028U - - Google Patents
Info
- Publication number
- JPH0243028U JPH0243028U JP12089088U JP12089088U JPH0243028U JP H0243028 U JPH0243028 U JP H0243028U JP 12089088 U JP12089088 U JP 12089088U JP 12089088 U JP12089088 U JP 12089088U JP H0243028 U JPH0243028 U JP H0243028U
- Authority
- JP
- Japan
- Prior art keywords
- reference power
- switch
- converter
- power supply
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 9
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第1図はこの考案の一実施例を示す概観図、第
2図aは従来のデイジタル−アナログ変換装置の
入出力特性図、第2図bは本考案のデイジタル−
アナログ変換装置の入出力特性図、第3図aは入
力Mbitデイジタル信号のフオーマツト図、第
3図bは入力Mbitデイジタル信号が+|2(
N−1)−1|時の上位Nbitのフオーマツト
図、第3図cは下位Nbitのフオーマツト図、
第3図dは入力Mbitデイジタル信号が−|2
(N−1)|時の上位Nbitのフオーマツト図
、第3図eは下位Nbitのフオーマツト図、第
4図は従来のデイジタル−アナログ変換装置の概
観図である。
図において、1はNbitD/Aコンバータ、
2,7は基準電源、3は入力Mbitデイジタル
信号、4は出力アナログ信号、5は乗算器、6は
スイツチ、8はアナログスイツチ、9は判定器で
ある。なお、各図中同一符号は同一または相当部
分を示す。
FIG. 1 is an overview diagram showing an embodiment of this invention, FIG. 2a is an input/output characteristic diagram of a conventional digital-to-analog converter, and FIG.
The input/output characteristic diagram of the analog converter is shown in FIG. 3a, the format diagram of the input Mbit digital signal, and FIG.
N-1)-1|, the format diagram of the upper N bits, FIG. 3c is the format diagram of the lower N bits,
Figure 3d shows that the input Mbit digital signal is -|2
(N-1)| FIG. 3e is a format diagram of the upper N bits, FIG. 3 is a format diagram of the lower N bits, and FIG. 4 is an overview diagram of a conventional digital-to-analog converter. In the figure, 1 is an Nbit D/A converter,
2 and 7 are reference power supplies, 3 is an input Mbit digital signal, 4 is an output analog signal, 5 is a multiplier, 6 is a switch, 8 is an analog switch, and 9 is a determiner. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
N)倍する乗算器、この乗算器の出力信号と上記
入力Mbitデイジタル信号を切り換えるスイツ
チ、このスイツチの出力信号をD/A変換し出力
アナログ信号を生成させるNbitD/Aコンバ
ータ、このNbitD/Aコンバータの基準電源
電圧を発生させる基準電源、この基準電源の1/2
(M−N)倍の電圧を発生させる基準電源、上記
2つの基準電源の出力電圧を切り換え上記Nbi
tD/Aコンバータの基準電源とするアナログス
イツチ、上記入力Mbitデイジタル信号の大き
さを判定し上記スイツチ及びアナログスイツチの
接点を制御する判定器とを備えたデイジタル−ア
ナログ変換装置。 One input Mbit digital signal is converted into 2 (M-
N) a multiplier that multiplies, a switch that switches between the output signal of this multiplier and the input Mbit digital signal, an Nbit D/A converter that converts the output signal of this switch to D/A and generates an output analog signal, and this Nbit D/A converter. A reference power supply that generates a reference power supply voltage of 1/2 of this reference power supply.
A reference power supply that generates (M-N) times the voltage, and switches the output voltage of the two reference power supplies above to the Nbi
A digital-to-analog converter comprising: an analog switch used as a reference power source for a tD/A converter; and a determiner that determines the magnitude of the input Mbit digital signal and controls contacts of the switch and the analog switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12089088U JPH0243028U (en) | 1988-09-14 | 1988-09-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12089088U JPH0243028U (en) | 1988-09-14 | 1988-09-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0243028U true JPH0243028U (en) | 1990-03-26 |
Family
ID=31367407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12089088U Pending JPH0243028U (en) | 1988-09-14 | 1988-09-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0243028U (en) |
-
1988
- 1988-09-14 JP JP12089088U patent/JPH0243028U/ja active Pending