JPH0243343B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a master slice type semiconductor device, and the present invention relates to a master slice type semiconductor device, in which the present invention relates to a semiconductor device of the master slice type, and is provided for use among output transistors formed on a semiconductor substrate in a number equal to or greater than the number of input/output pads. The present invention relates to a semiconductor device using a transistor that is not used as a diode for preventing electrostatic damage.

As the integration density of master slice semiconductor devices formed on semiconductor chips increases, the integrated circuit patterns thereof tend to become increasingly finer. As a result, the electrostatic breakdown voltage of the integrated circuit element decreases, and countermeasures have become necessary.

[Conventional technology]

As a means to meet such demands, it is also conceivable to provide special elements or circuits for this purpose within the integrated circuit. These elements or circuits are other than those required to realize the original functions formed in the integrated circuit.

[Problems to be solved by the invention]

By providing the above-mentioned elements or circuits, it is possible to prevent electrostatic damage to the elements. However, since the above-mentioned elements and circuits are only for preventing electrostatic discharge damage, there is a problem in that the provision of such elements or circuits will produce results that are contrary to the high degree of integration intended by the master slice method. be.

The present invention was created in view of these problems, and an object of the present invention is to provide a semiconductor device that can increase the usage rate of elements without reducing the integration density, and can also prevent electrostatic damage. purpose.

[Means to solve the problem]

The present invention provides a master slice type semiconductor device having input/output pads around a semiconductor chip and a plurality of gates provided inside the semiconductor chip, in which a number of output transistors equal to or greater than the number of input/output pads are connected to the input/output pads. Connect the base of the transistor that is not used among the output transistors to the wiring that connects the input pad of the input/output pad and the gate, and connect the collector to a specified power supply. Then, the unused output transistor is connected as a diode for preventing electrostatic damage.

[Effect]

The base of the output transistor, which is formed on a semiconductor chip according to the master slice method and is not used in the circuit configuration, is connected to the wiring between the input pad and the gate, and the collector of the output transistor is connected to a specified power supply. Even if an abnormal voltage such as a surge is input to the input pad, the voltage is reduced to a low level by the output transistor and is applied to the gate.

Therefore, the gate formed by miniaturization using the master slicing method can be protected from the abnormal voltage.

〔Example〕

FIG. 1 shows an embodiment of the invention. Reference numeral 1 denotes a semiconductor chip, around which input/output pads 2 are arranged. An output transistor 3 is provided in advance inside these input/output pads. Generally, in a circuit configuration using the master slice method, the number of transistors 3 in the master pattern is set to be greater than the number of input/output pads (pins) in order to increase the degree of freedom. Inside where these output transistors are arranged,
A required number of gates or cells 4 are formed.

An output transistor 6 is connected between the output circuit of these gates and an output pad, for example 5.

In addition to the output transistors connected in this way, of the output transistors that were not used in the circuit configuration, the redundant output transistor 3 located near the input pad connects the input pad 6 and gate 4. It is diode-connected and connected to the wiring 7 between them. If the gate 4 is of a type operated with a negative drive voltage, the terminal 8 of the diode-connected transistor 3 on the opposite side from the connection end to the wiring 7 is connected to a predetermined reference voltage, e.g. Connected to ground potential.

Connection of such a diode-connected output transistor to the wiring between the input pad and the gate is made for each input pad required.

With such a circuit configuration, even if an abnormal voltage such as a surge enters from the input pad, the capacitance component of the diode-connected transistor 3 acts on the abnormal voltage and relieves it and supplies it to the input gate. It is possible to prevent electrostatic damage from occurring in the input gate 4 whose electrostatic breakdown voltage has decreased as a result of the electrostatic damage. This abnormal voltage mitigation effect is produced by current flowing through the collector, which forms a junction with the base over a wide area, and is therefore effective even against relatively high abnormal voltages. Such enhancement of electrostatic breakdown voltage is achieved by increasing the number of diode-connected transistors as described above.
Since such a transistor is located near the input port, it is easy to connect it.

This enhancement of electrostatic breakdown voltage is achieved by using output transistors that are pre-formed on the chip, which increases the utilization of elements on the chip and facilitates the miniaturization of integrated circuits. It can also be promoted.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the output transistor, which is pre-formed on the semiconductor substrate of the semiconductor device using the master slicing method, is used as the diode for preventing electrostatic damage, so the element usage rate is improved. By strengthening the electrostatic breakdown voltage with the diode, it will be possible to further promote the miniaturization of integrated circuits. Such advantages can be easily enhanced within the permissible increase in the number of diodes. Also,
The above-mentioned effects can be obtained while the diode connection described above is facilitated.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention. In FIG. 1, 1 is a semiconductor chip, 2 is an input/output pad, 3 is an output transistor, 4 is a gate, 6 is an input pad among the input/output pads, and 7 is a wiring.

Claims (1)

[Claims] 1. In a master slice type semiconductor device having an input/output pad around a semiconductor chip and a plurality of gates provided inside the semiconductor chip, a number of output transistors equal to or greater than the number of input/output pads are connected between the input/output pads and gates. In the wiring that connects the input pad and gate of the input/output pads,
The bases of the unused output transistors are connected, the collectors are connected to a predetermined power source, and the unused output transistors are connected as a diode for preventing electrostatic damage. semiconductor device.