JPH0243609A - Clock control system - Google Patents

Abstract

PURPOSE:To execute the high speed and the low energy consumption by comparing a code stored in a register group and a code on the data bus of a computer system and outputting the clock signal of frequency instructed by the information. CONSTITUTION:Code comparing circuits 3A and 3B always compare the instruction code of a computer system on a system bus 7 and a code stored in code storing register groups 4A and 4B and detects the coincidence. The code comparing circuits 3A and 3B, when the coincidence of the code is detected, output the information to instruct the frequency corresponding to the code to variable frequency generating circuits 2A and 2B. Clock signals (a) and (b) which are output clocks become a necessary fundamental clock with control circuit groups 5 and 6. Since the frequency of the clock signal of the computer system is timely variable, the optimum and economical energy consumption can be realized and the high speed use and low energy consumption can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock control method for a computer system, and particularly to a clock control method for a computer system in which the instruction cycle time of a microprocessor in a computer system is determined by a basic tarok. Regarding.

[Conventional technology]

Some computer systems generate a basic clock using a basic clock generation circuit. An example of such a computer system is shown in FIG. As shown in FIG. 5, the basic clock d generated by the basic clock generation circuit 51 is divided by the frequency dividing circuit 52, and the clock e,
It becomes f. The clock e is output to a computer system circuit 53 consisting of a CPU (central processing unit)/interrupt control circuit, and the clock f is output to a control circuit group 54 including a timer/clock control circuit and an input/output control circuit. Ru.

In this prior art computer system,
Generally, the basic clock of a computer system is fixed from the time the power is turned on (initialization). There is also a computer system that can use two types of basic clocks, but the system starts up from initialization after switching the basic clocks using a switch circuit.

[Problem to be solved by the invention]

In the conventional computer system described above, the basic clock of the computer system is fixed when in operation. In consideration of maximum utilization of the computer system, a basic clock with approximately the maximum frequency within the standard range is used. Therefore, computer systems operate with the same clock frequency even when in standby mode or in use at low speeds, and computer systems whose power consumption increases in proportion to the operating frequency have the disadvantage of high power consumption. be.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate such drawbacks and provide a clock control method that can vary the frequency of the basic clock.

[Means to solve the problem]

The present invention is a clock control method for varying the frequency of a clock signal of a computer system, and stores a code corresponding to the clock signal that is a trigger for programmably controlling the frequency of the clock signal. a comparing unit that constantly compares a register group, a code stored in the register group, and a code on a data bus of the computer system, and outputs information indicating a frequency when a match is detected; The invention is characterized in that it has a generating section that outputs a clock signal of a frequency specified by the information.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This clock control method uses a clock signal a that determines the instruction cycle time of the computer system to the computer system circuit 5 consisting of a CPU/interrupt control circuit, and a control circuit group such as a timer control circuit and an input/output control circuit group. The clock signal S to 6 is variably outputted as a plurality of clock signals at appropriate times. This clock control method consists of a basic clock generation circuit 1 and a variable frequency generation circuit 2.
A, 2B, code comparison circuits 3A, 3B, and code storage register groups 4A, 4B.

In a computer system having such a configuration, the basic clock generation circuit 1 is connected to the next stage variable frequency generation circuit 2A.
, 2B. Note that if each of the variable frequency generation circuits 2A and 2B has a lock generation source if necessary, the basic clock generation circuit 1 becomes unnecessary.

The code storage register sections 4A and 4B receive a clock signal a,
It is made up of a group of registers that store codes (information) such as instruction codes or memory address codes that serve as triggers for programmably variable control of the frequency of b. The codes stored in the code storage register groups 4A and 4B correspond to the clock signals a and b, respectively, and are used to define the output frequency values of the clock signals a and b. The contents of the code storage register groups 4A and 4B can be arbitrarily rewritten via the system bus 7.

Code comparison circuits 3A and 3B compare codes such as computer system instruction codes or memory address codes on system bus 7 with code storage register groups 4A and 4.
A match is detected by constantly comparing the code stored in B. When code comparison circuits 3A and 3B detect a code match, they output information indicating a frequency corresponding to this code to variable frequency generation circuits 2A and 2B.

The variable frequency generation circuits 2A and 2B are the code comparison circuit 3A.
, 3B, the circuit generates clock signals a and b of arbitrary frequencies individually determined in advance.

Clock signal a, which is one output clock, becomes a basic clock (CPU clock) that determines the instruction cycle time to computer system circuit 5, and clock signal a, which is the other output clock, is a basic clock necessary for control circuit group 6. becomes.

Next, the operation of this embodiment will be described with reference to the timing diagram of FIG. 2 in the case where the frequencies of clock signals a and b are variably controlled by instruction codes of a computer system.

The code storage register group 4A includes a variable frequency generation circuit 2.
An instruction code that defines the output frequency of the clock signal a output from A is stored.

That is, the code storage register group 4A stores an instruction code corresponding to the clock signal a, which is a trigger for programmably controlling the frequency of the clock signal a. Note that in this embodiment, in instruction code A,
The clock signal output from the variable frequency generation circuit 2A corresponds to the low speed operation of the computer system 5, and in instruction code A2, the clock signal output from the variable frequency generation circuit 2A corresponds to the high speed operation of the computer system 5. ing.

On the other hand, there is an output port in the instruction code on the system bus 7.
Contains 7 variable control instruction codes.

That is, instruction codes including instruction codes A, . . . A2 are transmitted on the system bus 7 of the computer system. The code comparison circuit 3A constantly compares the instruction code on the system bus 7 with the instruction code stored in the code storage register group 4A. Then, when the instruction code A1 is detected by the code comparison circuit 3A, the code comparison circuit 3A outputs information indicating the frequency of low-speed operation to the variable frequency generation circuit 2A. Based on this information, the variable frequency generation circuit 2A outputs a clock signal a during low-speed operation to the computer system circuit 5. When the instruction code A2 is detected by the code comparison circuit 3A, the code comparison circuit 3A outputs information indicating the frequency of high-speed operation to the variable frequency generation circuit 2A. Based on this information, the variable frequency generation circuit 2A outputs a clock signal a during high-speed operation to the computer system circuit 5.

Similarly, the code storage register group 4B stores an instruction code that defines the output frequency of the clock signal output from the variable frequency generation circuit 2B. In this embodiment, in the instruction code B, the clock signal output from the variable frequency generation circuit 2B corresponds to the clock timing B of the control circuit group 6, and in the instruction code B2, the clock signal output from the variable frequency generation circuit 2B corresponds to the clock timing B of the control circuit group 6. The clock signal corresponds to clock timing A of the control circuit group.

On the other hand, instruction codes including instruction codes B, , B, are being transmitted on the system bus 7 of the computer system. The code comparison circuit 3B constantly compares the instruction code on the system bus 7 with the instruction code stored in the code storage register group 4B. And instruction code B
, is detected in the code comparison circuit 3B, the code comparison circuit 3B outputs information indicating the frequency of the clock timing B to the variable frequency generation circuit 2B.

Based on this information, the variable frequency generation circuit 2B outputs a clock signal at clock timing B to the computer system circuit 5. Instruction code B2 is code comparison circuit 3
When detected at B, the code comparison circuit 3B outputs information indicating the frequency of clock timing A to the variable frequency generation circuit 2B. Based on this information, the variable frequency generation circuit 2B outputs a clock signal at clock timing A to the control circuit group 6.

In this manner, according to the present embodiment, when the computer system is in a sufficiently used state with low-speed operation such as standby or light processing load operation, timely (time-sharing)
, CPU clock, etc. can be varied.

FIG. 3 is a flowchart showing an example of software control using the present invention. In FIG. 3, first, in the standby state, low speed is selected and idle processing is performed. Next, when high speed is selected instead of standby state, high speed processing is performed, and high speed is also selected at an appropriate time. Similarly, if low speed is selected instead of the standby state, low speed processing is performed, but low speed is also selected at an appropriate time. In this way, according to this software control, the operating speed can be varied as appropriate depending on the operating state inside the computer system.

FIG. 4 is a diagram showing an example of an application in which the present invention is used to operate a plurality of application software at an operating speed suitable for the purpose. In FIG. 4, the clock signal a is variably controlled to be a high speed clock, a medium speed clock, or a low speed clock depending on the memory address areas where application software (programs) A, B, and C are resident (stored). Similarly, the clock signal is variably controlled to timing A, timing B, and timing C.

〔Effect of the invention〕

As explained above, the present invention allows the frequency of the clock signal of a computer system to be varied at any time, so it is possible to realize optimal and economical power consumption in computer systems, etc., where power consumption increases in proportion to operating speed. In battery-powered computer systems, etc., it has the effect of realizing high-speed usage and low power consumption, which are the most important improvements in performance.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram of the embodiment shown in FIG. 1, and FIG. 3 is an example of software control using the present invention. Flowchart; FIG. 4 is a diagram showing an example of an application in which the present invention is used to operate multiple application software at an operating speed suitable for the purpose; FIG. 5 is a block diagram showing an example of a conventional computer system. It is. ■...Basic clock generation circuit 2A, 2B...Variable frequency generation circuit 3A, 3B...Code comparison circuit 4A, 4B...Code storage register group 5...Computer system circuit 6. ... Control circuit group agent Yoshiyuki Iwasa, patent attorney Memory address map Flora Kui language 0. RiD Tsukui i-'3b Figure 4

Claims (1)

[Claims] (1) A clock control method that varies the frequency of the clock signal of a computer system, and a register that stores a code corresponding to this clock signal that is a trigger for programmably variable control of the frequency of the clock signal. a comparison unit that constantly compares the code stored in the register group, the code stored in the register group, and the code on the data bus of the computer system, and outputs information indicating a frequency when a match is detected; and information from the comparison unit. 1. A clock control method, comprising: a generating section that outputs a clock signal having a frequency specified by the clock control method.