JPH0243629A - Stack pointer control system - Google Patents

Abstract

PURPOSE:To attain the high speed at the time of a continuous stack operation by providing a temporary second stack pointer at an address preparing part. CONSTITUTION:A first stack pointer 4 to store an address for the stack operation and a second stack pointer 3 are provided, the contents are written in the second stack pointer 3 in response to the updating of the contents of the first stack pointer 4 and the contents of the second stack pointer 3 are updated. Further, an effective bit 5 storing means to show the effectiveness ineffectiveness of the contents of the second stack pointer 3 and a bit rewriting means to make an effective bit 5 storing means into a bit to show the ineffectiveness in response to the updating of the contents of the first stack pointer 4 and make an effective bit 5 storing means into a bit to show effectiveness when the writing of the contents of the second stack pointer 3 is executed are provided, and when an effective bit 5 shows the effectiveness, the address preparation is executed with the contents of the stack pointer 3, and when the effective bit 5 shows the ineffectiveness, the address preparation is executed with the contents of the first stack pointer 4. Thus, the continuous stack operation can be executed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stack pointer control method, and more particularly to a stack pointer control method for generating addresses necessary for stack operations.

Wataru Ryomizu Conventionally, in order to perform a stack operation, an address is generated in an address generation section using the value of the stack pointer of an arithmetic execution section, and the stack operation is performed using this address.

Therefore, in consecutive stack operations, it is necessary to wait until the update of the stack pointer in the arithmetic execution unit is completed before generating an address for the next stack operation. Therefore, the address generation unit has a disadvantage that the address generation process is stopped while the stack pointer is updated.

Good friend! Therefore, the present invention has been made to solve the drawbacks of the prior art, and its purpose is to provide a stack pointer control method that allows continuous stack operations to be performed at high speed. It is about providing.

A stack pointer control method according to the present invention includes a first stack pointer that stores an address for stack operation, a second stack pointer that is different from this stack pointer, and a stack pointer that stores the contents of the first stack pointer. writing means for writing the contents of the first stack pointer into the second stack pointer in response to an update; updating means for updating the contents of the second stack pointer; and validating or invalidating the contents of the second stack pointer. effective bit storage means for indicating;
In response to updating the contents of the first stack pointer, the valid bit storage means is set to a bit indicating invalidity, and when the contents of the second stack pointer are written by the writing means, the valid bit storage means is set to a bit indicating invalidity. a bit rewriting means for generating a bit indicating validity, generating an address using the contents of the second stack pointer when the valid bit indicates valid; and generating an address using the contents of the second stack pointer when the valid bit indicates invalid; The feature is that the address is generated using the contents of the stack pointer.

Fire painting Next, embodiments of the present invention will be described with reference to the drawings.

Figure 1 is a block diagram of one embodiment of the present invention! ).

Address generation and operation execution are processed in a pipeline system, and the instructions sent from the instruction read fillio enter the decoder 7 of the address generation unit 1 and the instruction queue 11 at the same time, and after passing through several stages of the instruction queue 11. , enters the decoder 8 of the calculation execution unit 2. The pipeline control mechanism 9 controls the execution timing of address generation and arithmetic execution.

The pipeline control fi structure 9 includes a semaphore 12 for managing hazards of the stack pointer 4. The value of this semaphore is 0 at the beginning, and when an instruction to change the value of the stack pointer 4 enters the decoder 7 of the address generation section 1, the value of the semaphore 12 is incremented by 1, and when it enters the decoder 8 of the operation execution section 2, the semaphore The value of 12 is controlled to be -1.

Valid pins 1 to 5 indicating the presence and dynamicity of temporary stack pointer 3
is controlled by an instruction, and this valid bit 5 is set to O when an instruction to store a value pointing to a new stack in the stack pointer 4 enters the decoder 7 of the address generation unit 1, and the valid bit 5 is set to O when the instruction to store a value pointing to a new stack in the stack pointer 4 enters the decoder 7 of the address generation unit 1. After storing the value of , it is set to 1.

In the update mechanism 6, the value of the temporary stack pointer 3 or stack pointer 4 used to generate the address for stack operation is entered into the adder 15 via the selector 14 and updated. The update value 13 is generated based on the type of stack operation, the length of data, etc.

The flow of execution of stack manipulation instructions will be described below. When a stack manipulation instruction from the instruction reading mechanism 10 enters the decoder 7 of the address generation section 1, the value of the valid bit 5 is first checked. If the value of valid bit 5 is 1, the value of temporary stack pointer 3 is used for address generation. At this time, the value of the temporary stack pointer 3 is updated by the update mechanism 61 and stored in the temporary stack pointer 3 again.

If the value of the valid bit 5 is O, the value of the stack pointer 4 of the arithmetic execution unit 2 is used for address generation. The value of the stack pointer 4 used to generate this address is updated by the update mechanism 6 and stored in the temporary stack pointer 3. At this time, the value of valid bit 5 is set to 1. If the value of the semaphore 12 for the stack pointer 4 of the pipeline control mechanism 9 is not 0 when the value of the valid bit 5 is 0,
After waiting for the value of the semaphore 12 to become 0, the process described above when the value of the valid bit is 0 is executed.

With the above configuration, addresses can be generated in successive stack operations using the temporary stack pointer 3 and the update mechanism 6, making it possible to perform advanced stack operations.

As described above, according to the present invention, a temporary second stack pointer is provided in the address generation section, and in the case of continuous stack operations, this temporary stack pointer is used. , which has the effect of providing high speed in the case of continuous stack operations.

[Brief explanation of the drawing]

The figure is a system block diagram of an embodiment of the present invention. Explanation of symbols of main parts 1...Address generation section 2... Arithmetic execution unit 3...Temporary stack pointer 4...Stack pointer 5... Valid bit 6...Update mechanism

Claims (1)

[Claims] (1) A first stack pointer that stores an address for stack operations, and a second stack pointer that is different from this stack pointer.
a tack pointer; a writing means for writing the contents of the first stack pointer into the second stack pointer in response to an update of the contents of the first stack pointer; and an updating means for updating the contents of the second stack pointer. and the second
a valid bit storage means for indicating whether the contents of the stack pointer are valid or invalid; and responsive to updating of the contents of the first stack pointer, the valid bit storage means is set to a bit indicating invalidity; bit rewriting means for changing the valid bit storage means to a bit indicating validity when the contents of the stack pointer are written;
When the valid bit indicates valid, the contents of the second stack pointer are used to generate the address, and when the valid bit indicates invalid, the contents of the first stack pointer are used to generate the address. A stack pointer control method characterized by: