JPH0243633A - Parity checking device - Google Patents

Abstract

PURPOSE:To shorten processing time to execute parity checking by executing the parity checking with a hardware. CONSTITUTION:When a word including the data to be parity-checked is designated, the address of the control information of data is read from a control information address holding means and the address of the head data of the word including the data is read from a data address holding means. By the address of the head data and the starting position of the data out of read control information, the address of the data to be parity-checked is obtained and by the address and the width of the data out of the control information, the data are read from a memory by a data selecting part 5. For the selected data to be parity- checked, the parity checking is executed by the even number and odd number parity checking instruction read by the data selecting part 5. Thus, the processing time can be shortened more than the execution of the parity checking with the software.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a failure handling device for diagnosing and recovering an information processing device, and particularly to a parity check method performed when diagnosing an information processing device.

[Prior Art] Conventionally, in the parity check method performed when diagnosing information processing equipment, the parity check is performed by software. Therefore, the data to be parity checked and the parity accompanying it are extracted, and the extracted data is The validity of the data to be parity checked was checked by taking the exclusive OR of all the constituent bits.

[Problems to be Solved by the Invention] In the above-described conventional parity check method performed during diagnosis of an information processing device, the parity check of the data of the information processing device is performed by software, so the parity check requires a considerable amount of processing time. There is a disadvantage that this processing time occupies a large portion of the time required for troubleshooting.

[Means to solve the problem]

The parity check device of the present invention comprises: word data including data to be parity checked;
In an information processing device having a memory storing a plurality of control information including a start position of data included in each word, a data width, and an even/odd parity check instruction, the beginning of the word stored in the memory a plurality of data address holding means for holding addresses of data; a control information address holding means for holding addresses of control information of data stored in the memory and included in each word; and a word containing data to be parity checked. is specified, the address of the control information of this data is read from the control information address holding means, the control information of this address is read from the memory, and the address of the first data of the word containing this data is read from the data address holding means. The address of the data to be parity checked is determined based on the address of this first data and the start position of the data among the read control information, and this data is stored in the memory according to this address and the width of the data among this control information. a parity check section that performs a parity check on the data to be parity checked selected by the data selection section according to an even/odd parity check instruction read by the data selection section; A special register that can hold the parity check result and show it to software, and a parity check instruction that specifies the data address holding means and control information address holding means of the data to be parity checked are input to the data selection section. and a control unit that specifies the word of data to be parity checked.

[Operation] Performing a parity check using hardware reduces processing time compared to performing a parity check using software.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the parity check device of the present invention, and FIG. 2 (1) is a memory 1 of the information processing device.
Figure 2 shows the format of data stored in
FIGS. (2) and (3) are diagrams showing the format of data selected by the data selection section 4.

The parity check device 2 of this embodiment includes general-purpose register groups 3 and 4, a data selection section 5, a parity check section 6, a special register 7, and a control section 8. The memory 1 stores data of each word containing data to be parity checked, and corresponding to the data of each word, a plurality of data including the start position and bit width of the data included in each word and even/odd parity check instructions. control information is stored. The general-purpose register group 3 is composed of a plurality of general-purpose registers, and holds the address of the first data of each word stored in the memory 1. The general-purpose register group 4 is composed of a plurality of general-purpose registers, and holds the address of control information of data included in each word in correspondence with the address of the first data of each word. When a word containing data to be parity checked is specified, the data selection unit 5 reads the address of the control information of the data from the general-purpose register group 4,
The control information of this address is read from the memory l, the address of the first data of the word is read from the general-purpose register group 3, and the parity should be checked based on the address of this first data and the start position of the data among the read control information. The parity check section 6 obtains the address of the data and reads the data from the memory 1 based on this address and the width of the data among the control information. The special register 7, which performs a parity check based on an even/odd parity check instruction, can hold the result of the parity check by the parity check section 6 and show it to software. The control unit 8 inputs a parity check instruction specifying a general-purpose register in the general-purpose register groups 3 and 4, and specifies, to the data selection unit 5, a word of data to be parity-checked. The format of the parity check instruction is ropcA,,BJ, with roPCJ indicating that it is a parity check instruction, and operand A.
, B. Operands A and B specify each general-purpose register in general-purpose register group 3.4.

Next, the operation of this embodiment will be explained.

Now, when the information processing device fails, the data a, b, c (consisting of Ci and C2), and d to be parity checked are the second
As shown in Figure (1), one word of data is stored in memory 1, consisting of data a, b and C1.
The address within is general register GRI of general register group 3.
, data a.

It is assumed that the addresses in the memory 1 of control information b and c are stored in the general-purpose register GR2 of the general-purpose register group 4. A parity check command rOPc is sent to the control unit 8.
When GRI and GR2J are input, the data selection unit 5 selects data a.

The address of l word data (FIG. 2 (1)) consisting of data b, C1 is read from general register GRI, and data a
, b, and cl are read from the general-purpose register GR2.

Then, the data selection unit 5 selects data a and b.

The control information for each word cl is read from memory 1, and data a is read from memory l from among this one word of data, depending on the start position and bit width of data a within this word (see Figure 2 (2). ) ), a parity check is performed on this data a by a parity check unit 6 according to an even/odd parity check instruction sent from a data selection unit 5 together with data a, and the parity check result is held in a special register 7. Ru. In this way,
The parity check for data a is completed.

Next, for data b, data b is selected from data a, b, and C1 by the data selection section 5, and a parity check is performed by repeating the same operation as for data a described above.

Next, regarding the data C to be parity-checked (FIG. 2 (1)) stored across two words, the data C1 read out first by the data selection section 5 and the data C2 read out next. As a result, data C is generated as shown in FIG. 2 (3), and thereafter, validation and checking are performed in the same manner as in the case of data a described above.

Next, the parity check for data d is performed in the same way as for data a.

〔Effect of the invention〕

As described above, the present invention has the effect of shortening the processing time for parity checking by performing parity check using hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the parity check device of the present invention, and FIG. 2 (1) is a memory 1 of the information processing device.
Figure 2 shows the format of data stored in
FIGS. (2) and (3) are diagrams showing the format of data selected by the data selection section 5. 1...Memory, 2...Parity check device, 3
4... General-purpose register group, 5... Data selection section, 6...
・・・・・・Parity check section, 7・・・・・・
・・・・・・Special register, 8・・・・・・・・・・・・
・Control unit.

Claims (1)

[Claims] 1. Storing a plurality of control information consisting of word data including data to be parity checked, the start position of data included in each word, data width, and even/odd parity check instructions. an information processing device having a memory, comprising: a plurality of data address holding means for holding addresses of leading data of words stored in the memory; and addresses of control information of data stored in the memory and included in each word. control information address holding means for holding a parity check; and when a word containing data to be parity checked is specified, an address of control information of the data is read from the control information address holding means, and control information of the address is read from the memory. read out the address of the first data of the word containing the data from the data address holding means, and find the address of the data to be parity checked based on the address of the first data and the start position of the data in the read control information. a data selection section that reads the data from the memory according to the data width of the address and the control information; and a data selection section that reads out the data to be parity checked selected by the data selection section. A parity check section that performs a parity check based on an even/odd parity check instruction, a special register that can hold the parity check result of the parity check section and show it to software, and a data address holding means for data to be parity checked. A parity check device comprising: a control section that inputs a parity check command specifying a control information address holding means and specifies a word of data to be parity-checked to a data selection section.