JPH0243634A - Information processor - Google Patents

Abstract

PURPOSE:To suppress the increase of a hardware quantity and to earlier detect the intermittent trouble at the time of diagnosing a collating circuit by operating a collating circuit to execute the diagnosis collation by the conditions different from ordinary ones. CONSTITUTION:The title processor includes a means to give special diagnosis data in place of the collating data to the second input of a collating circuit not to give the collating data out of a collating circuit 6 and means 15 and 17 to change the cycle of the action clock of the collating circuit to give the diagnosis data for a specified value, and these collating circuits are diagnosed in accordance with the collating result of the collating circuit to give the diagnosing data. Namely, all the same diagnosis data are simultaneously given to plural collating circuits which become the collation action time idle condition by the relation of the variable collating data quantity and an unchanged collating circuit number, the diagnosis collation is executed simultaneously with the ordinary collation, and it is checked whether or not the diagnosed result is the same by all collating circuit to execute the diagnosis collation. Thus, the on-line diagnosis to simultaneously execute the ordinary collating action and the diagnosing action can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and more particularly to a diagnostic method for a data verification processing device that performs normal verification and diagnostic verification to check for the presence or absence of a failure in a verification circuit.

As a conventional method for diagnosing the verification circuit in such a verification processing device, there are the following methods. There are methods such as providing a hardware check circuit in the verification circuit, duplicating the verification circuit, and a so-called patrol method in which a diagnostic routine is periodically executed by software.

The method of providing a hardware check circuit or the method of duplicating the verification circuit increases the amount of hardware;
In particular, the latter method has the disadvantage that it is particularly unsuitable in the case of an array structure having a plurality of matching circuits. Although the patrol method does not require an increase in hardware, it has the disadvantage that it is difficult to detect intermittent failures in which the verification circuit occasionally fails and recovers.

Therefore, the present invention was made to solve the drawbacks of the conventional ones, and its purpose is to suppress the increase in the amount of hardware while diagnosing the verification circuit. An object of the present invention is to provide an information processing device that can detect even intermittent failures early.

An information processing device according to the present invention includes a plurality of verification circuits each having a first and a second input, and verifying whether or not the data given to the re-inputs are equal. , a data collation in which search data is commonly given to each first input of the collation circuit, and collation data equal to the search data is searched for by sequentially supplying a large number of collation data to the second input. An information processing device that adopts a method,
Means for supplying specific diagnostic data in place of the verification data to the second input of the verification circuit to which the verification data is not provided among the verification circuits, and an operation clock of the verification circuit to which the diagnostic data is supplied. The present invention is characterized in that it includes means for changing the cycle from a specified value, and that the verification circuits are diagnosed in accordance with the verification results of the verification circuits to which the diagnostic data is applied.

Another information processing device according to the present invention includes first and second information processing devices, respectively.
has a plurality of verification circuits for verifying whether or not the data given to the re-inputs are equal, and the search data is commonly given to the first input of each of the verification circuits. The information processing apparatus employs a data matching method in which matching data equal to the search data is searched for by sequentially applying a large number of matching data to the second input, wherein the matching data in the matching circuit is means for supplying specific diagnostic data in place of the verification data to the second input of the verification circuit to which the verification data is not provided; and means for changing the operating voltage of the verification circuit to which the diagnostic data is applied relative to a specified value. The present invention is characterized in that the verification circuits are diagnosed in accordance with the verification results of the verification circuits to which the diagnostic data is given.

Example Embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The storage device 1 stores search data and verification data. The storage device 2 stores diagnostic verification data used for diagnosis verification. Read data from the storage devices 1 and 2 is input to the common control unit 5 via buses 3 and 4. This common control unit 5 commonly controls the collation circuit 6 in which n collation circuits 6a to 6n having the same function are arranged in an array.
a flip-flop (hereinafter abbreviated as F/P) that instructs n to start transferring verification data; a circulation register that indicates a data transfer destination; a counter that indicates the number of remaining verification data;
It consists of a signal generation circuit that instructs all idle verification circuits to perform diagnostic verification, and a switching circuit that performs successive switching between storage devices 1 and 2.

On the other hand, each of the verification circuits 6a to 6n has a register for storing search data, a register for storing verification data, an F/F indicating that the contents of these registers are valid and a verification operation is possible, and a normal verification or verification circuit. Blocks 6a1 to 6nl consisting of mode F/Fs that instruct diagnostic verification, verification units 6a2 to 6n2, and block 6a that processes verification results.
It is composed of 3 to 6n3. Each of these matching circuits 6a~
6n and the common control unit 5 are connected by a common bus 9, respectively.

The verification circuit includes a plurality of clock signal lines 16 from the clock control circuit 15 and a control signal line 18 from the common control section.
As a result, a clock is supplied from the clock supply circuit 17 to each verification circuit as a clock signal line 19.

Further, the verification results of each of the verification circuits 6a to 6n are connected via a signal line 12 to a discrimination circuit 13 that discriminates the diagnostic verification results, and a discrimination signal 14 is output from this discrimination circuit 13.

With such a configuration, common search data (hereinafter referred to as "S data") is given to each collating circuit 6a to 6n in advance via the common bus 9. Verification data (hereinafter referred to as "F data J") is sequentially transferred to each verification circuit 6a-6Ω, and each verification circuit 6a-6
Normal verification is performed when F data is transferred to all of n.

During this F data transfer, if the number of F data becomes zero and any of the verification circuits 6a to 6n becomes vacant, the diagnostic data in the storage device 2 (hereinafter referred to as "S data") is transferred to the vacant verification circuit. be transferred. The verification circuit to which this S data is transferred performs diagnostic verification to determine whether or not a failure has occurred in the verification circuit. At this time, normal verification is performed in each verification circuit to which the F data has been transferred.

Either normal verification or diagnostic verification is performed in each of the verification circuits 6a to 6n, and information on the verification results is output to the discrimination circuit 13 via the signal line 12.

The determination circuit 13 determines whether or not two or more diagnostic verification results are the same, and outputs a determination signal 14.

The results of the normal verification are used by subsequent devices via the bus 11.

This will be explained in more detail. For ease of explanation, an example will be described in which there are four matching circuits arranged in an array.

FIG. 2 is a diagram showing an elliptical example of the main circuit of the common control section 5 shown in FIG. 1. The counter 18 is a counter that first sets the total number of F data to be compared with one S data, and is decremented by 1 each time one F data is transferred to each of the matching circuits 6a to 6d. Displays the number of F data. The contents 19 of this counter 18 are connected to a comparison circuit 21 via a signal line 20 and compared with zero. This comparison circuit 21
is compared with zero, and when the remaining number of F data becomes zero, the signal line 22 outputs logic "1".

Reference numeral 25 denotes a register, which is composed of four F/Fs 26 to 29 equal in number to the collation circuits 6a to 6d, and the contents thereof are configured to circulate through each of the F/Fs 26, 27, 28, and 29. This register 25 is for each F/F 26, 27, 28
．． The contents of 29 instruct data transfer to each of the matching circuits 6a to 6d via the signal lines 30, 31, 32, and 33.

Now, when transferring the first F data, "1" is set to F/F 26.
is set, instructing F data transfer to the collation circuit 6a, and thereafter, the content "1" of F/F 26 is circulated to each F/F 27, 28, 29, 26 every time F data is transferred, and the data transfer destination is with each matching circuit 6b, 6c, 6d, 6a (as shown).

When the F data is received by the corresponding verification circuit, the G signals 35, 36, 37.38 become "1", and all the verification circuits 6a to 6d become busy, and the G signal 35, 36, 37 becomes "1". When ゜38 is all “IJ,”
The gate 40 sets the signal line 41 to "1" and the signal line 42 to "1".
0", the F/F 43 is set to "1", the verification start signal line 44 becomes "IJ", and normal verification is performed. This verification result is output to the bus 11.

When this operation is repeated and the remaining number of F data becomes zero and "1" is output to the signal line 22, if at least one collation circuit has an empty F data, the signal line 42 becomes "1", and the S data transfer instruction signal 46 output from the gate 45 becomes "1". When this S data transfer instruction signal 46 becomes "IJ", the S data is transferred to the checking circuit in the empty state. be done.

Verification operation of all verification circuits is completed (signal lines 48, 49.50
．． 51 are all "1"), the gate 52 outputs "1" to the signal line 53, the F/F 54 is set to "1", and the F data transfer start signal 55 becomes "1".

Here, the number of F data becomes zero and the signal line 22 is “1”.
The contents of the register 25 at the time when "" is output are held, and when the F data transfer is restarted next time, a data transfer instruction is issued from this empty collation circuit, and thereafter a circulation instruction is issued in the same manner. Therefore, the F data transfer is always started from the verification circuit that has performed the diagnostic verification, thereby improving reliability and averaging the diagnostic operations for each verification circuit.

FIGS. 3 and 4 are block diagrams of one embodiment of the F data and S data reading section from the storage devices 1 and 2. FIG. The storage device 2 stores four different types of diagnostic verification data A, B, C, and D as S data, and when the S data transfer instruction signal 46 is "1", a pointer 56 indicating the S data storage address is stored. The data is read out by the gate 57 and transferred to the verification circuit via the bus 4.

On the other hand, when the signal line 58 is "1", the contents of the storage device 1 specified by the F data read address register 59 are transferred from the gate 60 to the verification circuit via the bus 3.

FIG. 5 is a block diagram of one embodiment of the verification circuit shown in FIG. 1, for example 6a. Registers 65 and 66 are connected to common bus 9
This is a register that stores S data, verification data, F data, and S data. F/F6
7 is an F/F for displaying a gee state when registers 65 and 66 have valid data. The F/F 68 is used to indicate that the verification data in the register 66 is S data. The gate 69 sets the F/F 67 via the gate 70 when the F/F 67 is "0" and the F data transfer start signal 55 is "1". The gate 71 is set when the F/F 67 is "0" and the S data transfer instruction signal 46 is "0".
1”, F/Fs 67 and 6 through gate 70
Set 8. By setting this F/F 68, it is displayed that the verification by the verification circuit is diagnostic verification.

The data in the registers 65 and 66 are sent to the matching circuit section 6a2, and when the matching start signal line 44 is rl, a matching operation is performed and the matching result is set in the F/F 72. At this time,
F/Fs 67 and 68 are reset by the collation end signal 73 generated at the same time. The output signal Dn of the F/F 68 and the output signal On of the F/F 72 are sent to the discrimination circuit 13, and the output signal of the F/F 67 is sent to the common control section 5.

FIG. 6 is a block diagram of one embodiment of the discriminating circuit 13 shown in FIG. 1. In FIG. Determination circuits 75a to 75d (duplex diagnostic circuits) that determine whether or not the diagnostic verification results Cn are the same are used to perform verification of the vacant state when there are three verification circuits in the vacant state. The output signal T of each of these discrimination circuits 74a to 74d and 75a to 75d is a discrimination circuit (triple diagnosis circuit) that discriminates whether each diagnosis result Cn performed in the circuit is the same or not.
n is "1" if the results are the same, "0" if the results are inconsistent
becomes.

The output signals T'n from each of the discrimination circuits 74a to 74d and 75a to 75d are outputted to the selection circuit 76 by Da,
One is selected according to the values of Db, Dc, and Dd, and the discrimination signal 14
occurs. Here, Da, Db.

Dc and Dd are output signals of the F/F 68 that output "1" when each of the verification circuits 6a to 6d is in a vacant state, S data is transferred, and diagnostic verification is performed.

The operation of the selection circuit 76 will be explained using the truth table shown in FIG. Da to Dd are output signals of the F/F 68, and T are output signals of each of the discrimination circuits 74 to 74d and 75a to 75d. In Fig. 7, Da, Db, Da, Dd-0000 Da, Db, Dc, Dd=OOOI Da, Db, Dc, Dd=OO10 Da Db, Dc, Dd=0100 Da, Db, Dc, Dd=1000 In this case, the diagnostic verification is performed by only one verification circuit, so the discrimination signal is always set to "1".

When Da, Db, Dc, Dd=0101 and Da, Db, Da, Dd=1010, it means that every other matching circuit is empty, and since this is an impossible state, the discrimination signal is always set to "
0".

When Da, Db, Da, Dd=Z 111, it indicates that all the verification circuits are in an empty state, and since diagnostic verification is not performed in this state, the 0 discrimination signal always sets the discrimination signal to "0". If 14 is "1", it is checked that it is in a normal state, and if it is "0", it is checked that it is in an invalid state.

It should be noted that when the discrimination signal 14 is "0", adding a locking function to the verification device will be effective in troubleshooting. Furthermore, the present invention becomes even more effective if the F data location and the number of collation circuits are appropriately set.

FIG. 8 is a configuration diagram of an embodiment of the clock control section 8@15 and the clock supply circuit 17 shown in FIG. 1. 1st
The control signals 18 in the figure are Da to Dd and E in FIG.
Corresponds to a to Bd. Also, the signal 19 in FIG. 1 is 6a to 6.
This corresponds to the clock of d. Signal lines Da to Dd and Ea
~Ed is the output signal of F/F 68 in FIG. When the verification circuit performs diagnostic verification, that is, F/
When the output signal Dn of F68 is "1", a diagnostic clock having a cycle other than the specified clock cycle for normal verification is supplied to the circuit to be verified. 7 in Figure 8
9a to 79d are OR gates.

FIG. 9 is a system block diagram of another embodiment of the present invention, in which parts equivalent to the embodiment of FIG. 1 are designated by the same reference numerals. To describe only the differences from the example in FIG. 1, each collation circuit operates with an operating voltage set by a control signal 91 sent from the common control section 5 to a voltage control 90. The voltage supply section 93 determines the value of the voltage to be supplied to each verification circuit based on the control signal 92 from the voltage circuit 90.

FIG. 10 is a configuration diagram of one embodiment of the voltage control circuit 90 shown in FIG. 9. Control signals 91 in FIG. 9 correspond to Da to Dd and Ea to Ed. In Figure 5, F/F 6
8, the voltage control circuit 90 in FIG. 7 sets the supply voltage level to a value different from the specified value, and the voltage is supplied via the voltage supply section 93 etc. Ru. The voltage control circuit 90 is configured using a relay or the like, and receives digital signals Da to Dd and "Ea".
~Ed into an analog signal 92. Voltage supply section 93
The receiver supplies operating dynamic pressure to each verification device individually.Normally, a specified operating voltage is supplied to each verification circuit, but for verification circuits that perform diagnostic verification,
An operating voltage other than the specified value is supplied.

In this way, by operating the verification circuit that performs diagnostic verification under conditions different from normal conditions (conditions such as clock cycle and operating voltage), a more aggressive diagnostic operation can be performed. Therefore, early detection of failures becomes possible by turning intermittent failures into fixed failures.

According to the present invention, there is an advantage that there is no need to add a diagnostic check circuit to each verification circuit, and there is no need to duplicate the verification circuits. In other words, the same diagnostic data is simultaneously applied to a plurality of verification circuits that are in an idle state during verification operation due to the relationship between the variable amount of verification data and the unchanging number of verification circuits.
Since we decided to perform diagnostic verification at the same time as normal verification and check whether the diagnostic results are the same in all the verification circuits that performed diagnostic verification, online Diagnosis can be made. Therefore, intermittent failures can be reduced without requiring special diagnostic time.

Furthermore, an increase in the amount of diagnostic hardware can be suppressed.

Furthermore, since the verification data is transferred to the verification circuit in a continuous manner, it has excellent effects such as being able to average out the diagnostic operations.

Further, by operating the verification circuit that performs diagnostic verification under conditions different from normal conditions, the diagnostic operation becomes more active, and if an intermittent failure becomes a fixed failure, there is an effect that failures can be detected early.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a specific example of the common control section, FIG. 3 is a diagram showing a specific example of the readout circuit of the storage device 2, and FIG. 4 is a diagram showing a specific example of the readout circuit of the storage device 2. FIG. 5 is a diagram showing a specific example of the readout circuit of the device 1, FIG. 5 is a diagram showing a specific example of the collation circuit, FIG. 6 is a diagram showing a specific example of the discrimination circuit, and FIG. 7 is a diagram showing a specific example of the selection circuit 76 in the discrimination circuit. A truth table showing the behavior,
FIG. 8 is a diagram showing a specific example of a clock control circuit, FIG. 9 is a system block diagram of another embodiment of the present invention, and FIG. 10 is a diagram showing a specific example of a voltage control circuit. 1.2...Storage device 5...Common control unit 6...Verification circuit 13...Discrimination circuit 15...Clock control circuit 17 ......Clock supply circuit 90...Voltage control circuit 93...Voltage supply section

Claims (2)

[Claims] (1) A plurality of verification circuits each having a first and a second input and verifying whether data given to both inputs are equal; An information processing device employing a data matching method in which search data is commonly given to the input, and matching data equal to the search data is searched for by sequentially giving a large number of matching data to the second input. , means for supplying specific diagnostic data in place of the verification data to the second input of the verification circuit to which the verification data is not provided among the verification circuits; and an operation clock of the verification circuit to which the diagnostic data is provided. and means for changing the cycle of the reference circuit from a specified value, and the information processing apparatus is characterized in that the verification circuit is diagnosed in accordance with the verification result of the verification circuit to which the diagnostic data is applied. (2) a plurality of verification circuits each having a first and a second input and verifying whether data given to both inputs are equal; The information processing apparatus employs a data matching method in which search data is commonly given to the input of the second input, and matching data equal to the search data is searched for by sequentially giving a large number of matching data to the second input. means for supplying specific diagnostic data in place of the verification data to the second input of the verification circuit to which the verification data is not provided among the verification circuits; and an operation of the verification circuit to which the diagnostic data is provided. 1. An information processing device comprising: means for changing a voltage with respect to a specified value; and a device for diagnosing a verification circuit to which the diagnostic data is applied in accordance with a verification result of the verification circuit.