JPH0243732A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0243732A JPH0243732A JP19376288A JP19376288A JPH0243732A JP H0243732 A JPH0243732 A JP H0243732A JP 19376288 A JP19376288 A JP 19376288A JP 19376288 A JP19376288 A JP 19376288A JP H0243732 A JPH0243732 A JP H0243732A
- Authority
- JP
- Japan
- Prior art keywords
- jcr
- chip
- substrate
- fixed
- junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、支持板上に固着した半導体基板表面のPN接
合露出部が、接合被覆樹脂(以下JCRと記す)を塗布
することによって保護される半導体装置の製造方法に関
する。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method in which the exposed PN junction portion of the surface of a semiconductor substrate fixed on a support plate is protected by applying a bond coating resin (hereinafter referred to as JCR). The present invention relates to a method for manufacturing a semiconductor device.
PN接合を利用した半導体装置の特性の劣化を防ぐため
には、半導体基板表面へのPN接合露出部およびその近
傍を外部雰囲気の影響から保護するためにパフシベーシ
ッンが必要であり、最も簡羊なパフシベーシタン方法と
してポリイミド樹脂などを半導体素体表面へ塗布する方
法が用いられている。第2図はそのような半導体装置の
一例を示し、シリコンチップ1はリードフレームのマウ
ント部2の上にはんだ3を用いてはんだ付けされている
。チフブ1の上面には、接続リード4の頭部41がやは
りはんだ付けされている。Siチフプlがプレーナ型で
PN接合が上面に露出している場合は、上面にJCR5
を塗布する。In order to prevent the characteristics of a semiconductor device using a PN junction from deteriorating, a puff-sealing method is necessary to protect the exposed portion of the PN-junction on the semiconductor substrate surface and its vicinity from the influence of the external atmosphere. As a method of applying polyimide resin or the like to the surface of the semiconductor element, a method is used. FIG. 2 shows an example of such a semiconductor device, in which a silicon chip 1 is soldered onto a mount portion 2 of a lead frame using a solder 3. As shown in FIG. The head 41 of the connection lead 4 is also soldered to the top surface of the chip 1. If the Si chip is planar and the PN junction is exposed on the top surface, JCR5 is placed on the top surface.
Apply.
第2図のようにSiチフプ1の上面にJCR5を塗布す
る場合、図示のようにJCRはチンブの側面に流れ出る
ため、上面の周辺部のJCR5が薄くなり、JCRが均
一に塗布されない欠点があった。その結果、PN接合露
出部上のJCR5が薄く、十分な保護作用が得られなか
ったり、不均一な厚さのJCRにより不均一な応力がS
iチフブ1に加わり、半導体装1の電気的特性および信
顛性に悪影響があった。When JCR5 is applied to the top surface of the Si chip 1 as shown in Figure 2, the JCR flows out to the side of the chip as shown in the figure, so the JCR5 around the top surface becomes thinner and there is a drawback that the JCR is not applied uniformly. Ta. As a result, the JCR5 on the exposed part of the PN junction is thin and cannot provide sufficient protection, and the JCR with uneven thickness causes uneven stress on the S.
In addition to the i-chip 1, the electrical characteristics and reliability of the semiconductor device 1 were adversely affected.
本発明の課題は、上記の欠点を除去し、半導体基板のP
N接合露出部表面にJCRを均一な厚さに塗布されてい
て、電気的特性および信幀性の高い半導体装置を提供す
ることにある。The object of the present invention is to eliminate the above-mentioned drawbacks and to
The object of the present invention is to provide a semiconductor device in which a JCR is coated to a uniform thickness on the surface of an exposed N-junction, and has high electrical characteristics and reliability.
上記の課題の解決のために、本発明は支持板上に固着さ
れた半導体基板の支持板への固着面と逆側の表面に、そ
の表面に露出したPN接合を覆うJCRを塗布する際に
、半導体基板の側面に接し、高さが基板表面より高い枠
体を備えるものとする。In order to solve the above problems, the present invention provides a method for applying JCR to cover the PN junction exposed on the surface of a semiconductor substrate fixed on a support plate, on the opposite side to the surface fixed to the support plate. , a frame body that is in contact with the side surface of the semiconductor substrate and whose height is higher than the surface of the substrate.
半導体基板の側面に接する枠体は、基板表面へ塗布する
JCRの側面への流出を阻止するため、基板周辺部まで
JCRを厚く、かつ均一に塗布できる。The frame body in contact with the side surface of the semiconductor substrate prevents the JCR applied to the substrate surface from flowing out to the side surface, so that the JCR can be applied thickly and uniformly to the periphery of the substrate.
第1図は本発明の一実施例を示すもので、第2図と共通
の部分には同一の符号が付されている。FIG. 1 shows an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals.
この実施例ではブレーナ型のSiチップ1の両面にリー
ドフレームマウント部2および接続リードをはんだ3で
固着したのち、Siチップ1の側面に接触する枠体6を
取付ける。しかし、枠体6をチップlのはんだ付けの前
にリードフレームに固定しておいてもよい、このあと、
Siチップlの表面にJCR5を塗布する。JCRは枠
体6の内周まで拡がり、そこで止められるので、JCR
5の厚さはSiチップ1の周辺まで均一であり、また任
意の厚さにすることができる。枠体をSiチップ1と支
持板2とのはんだ付は後に取付ける場合は、枠体の材料
はセラミック、プラスチックなどの絶縁体でも金属の何
れでもよい、はんだ付は前に取付ける場合は、はんだ付
温度で熱応力が生じないように支持板2と熱膨張係数の
近似した材料から作る必要がある。枠体6は、JCR塗
布後そのままの位置に残しておいてもよい、しかし取外
す必要がある場合は、JCRと濡れ性の良くない材料、
例えばセラミックで作った方が取外しやすい。In this embodiment, a lead frame mount portion 2 and connection leads are fixed to both sides of a brainer-type Si chip 1 with solder 3, and then a frame body 6 that contacts the side surface of the Si chip 1 is attached. However, the frame body 6 may be fixed to the lead frame before soldering the chip l.
Apply JCR5 to the surface of the Si chip l. The JCR expands to the inner circumference of the frame 6 and is stopped there, so the JCR
The thickness of the silicon chip 5 is uniform up to the periphery of the Si chip 1, and can be set to any desired thickness. If the frame is to be soldered to the Si chip 1 and the support plate 2 later, the material of the frame may be ceramic, plastic, or other insulating material, or metal. It is necessary to make it from a material with a coefficient of thermal expansion similar to that of the support plate 2 so that thermal stress does not occur due to temperature. The frame 6 may be left in place after applying the JCR, but if it needs to be removed, it may be removed using a material that does not have good wettability with the JCR.
For example, it is easier to remove if it is made of ceramic.
第3図は別の実施例を示し、リードフレームのマウント
部2にSiチップ1が嵌合し、31千ノブ1および片面
のはんだ3の厚さの和より深い四部7を形成しておく、
この凹部7の中にチップ1をはんだ付けしたのち、JC
R5の塗布を行えば、リードフレームのマウント部2が
枠体の作用も蓋ね、第7図の実施例と同様なJCRの均
一塗布が可能である。この実施例は、リードフレームの
形状の変更だけで容易に実施でき、枠体の取付は工程を
省略できる。FIG. 3 shows another embodiment, in which the Si chip 1 is fitted into the mount part 2 of the lead frame, and four parts 7 are formed which are deeper than the sum of the thicknesses of the 31,000 knobs 1 and the solder 3 on one side.
After soldering the chip 1 into this recess 7,
If R5 is applied, the mount portion 2 of the lead frame also functions as a frame, and uniform application of JCR similar to the embodiment shown in FIG. 7 is possible. This embodiment can be easily implemented by simply changing the shape of the lead frame, and the step of attaching the frame can be omitted.
本発明によれば、支持板上に固着された半導体基板の表
面に塗布するJCRを基板の側面に接する枠体により基
板側面へ流出するのを防ぐので、表面上に均一で任意の
厚さのJCRを塗布することが可能になる。これにより
半導体基板にJCRより加わる応力が均一となり、電気
的特性および信転性の向上した半導体装置が得られる。According to the present invention, since the JCR coated on the surface of the semiconductor substrate fixed on the support plate is prevented from flowing out to the side surface of the substrate by the frame that is in contact with the side surface of the substrate, a uniform and arbitrary thickness can be applied on the surface. It becomes possible to apply JCR. As a result, the stress applied to the semiconductor substrate by the JCR becomes uniform, and a semiconductor device with improved electrical characteristics and reliability can be obtained.
第1図は本発明の一実施例のJCR塗布後の断面図、第
2図は従来のJCR塗布後の断面図、第3図は本発明の
異なる実施例のJCRI布後の断面図である。
1:Siチップ、2:リードフレームマウント部、第1
図
第2図
第3図Fig. 1 is a cross-sectional view of one embodiment of the present invention after applying JCR, Fig. 2 is a cross-sectional view of a conventional JCR fabric after being applied, and Fig. 3 is a cross-sectional view of a different embodiment of the present invention after applying JCRI. . 1: Si chip, 2: Lead frame mount section, 1st
Figure 2 Figure 3
Claims (1)
面と逆側の表面に、その表面に露出したPN接合を覆う
接合被覆樹脂を塗布する際に、半導体基板側面に接し、
高さが基板表面より高い枠体を備えることを特徴とする
半導体装置の製造方法。1) When applying a bonding coating resin to cover the PN junction exposed on that surface to the surface of the semiconductor substrate fixed on the support plate opposite to the surface fixed to the support plate, contacting the side surface of the semiconductor substrate,
A method for manufacturing a semiconductor device, comprising a frame whose height is higher than the surface of a substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19376288A JPH0243732A (en) | 1988-08-03 | 1988-08-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19376288A JPH0243732A (en) | 1988-08-03 | 1988-08-03 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0243732A true JPH0243732A (en) | 1990-02-14 |
Family
ID=16313386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19376288A Pending JPH0243732A (en) | 1988-08-03 | 1988-08-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0243732A (en) |
-
1988
- 1988-08-03 JP JP19376288A patent/JPH0243732A/en active Pending
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