JPH0243740A - Manufacture of mos semiconductor element - Google Patents

Abstract

PURPOSE:To dispense with a resist coating process for the formation of a resist pattern and a photoetching process by a method wherein an oxide film left on a high-impurity region, which is formed for coming into contact to a source electrode, is used as a mask at the time of ion-implantation for forming source regions in addition to a gate oxide film and gate electrode patterns. CONSTITUTION:A second conductivity type high-impurity concentration region 21 is formed in the surface layer of a first conductivity type drain region (an Si substrate) 1 and thereafter, part of a surface oxide film 41 is made to remain only on a prescribed region of the region 21 and the rest of the film 41 is removed. Then, a second conductivity type channel region 22 is formed. Then, after a gate oxide film and a gate electrode layer are laminated, a patterning of gate electrodes 5 and a gate oxide film 4 under the electrodes 5 is performed leaving said remaining oxide film 41. Then, an ion-implantation for forming first conductivity type source regions 3 is performed using the electrodes 5, the gate oxide film pattern 4 and the remaining oxide film 41 as masks. After that, for example, the surface is covered with a PSG layer 9, a contact hole is formed in a photoetching process and a source electrode 6 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is directed to a power MOSFET or an insulated gate bipolar transistor (IGBT) in which a drain region surface layer of a first conductivity type is A source region of the first conductivity type is formed in the surface layer of the channel region, sandwiching the channel formation region between it and the drain layer, and a source region of the second conductivity type in the center of the channel region 91 is The present invention relates to a method of manufacturing a MOS semiconductor device in which a source electrode contacts an impurity region and a portion of a source layer.

[Conventional technology]

FIG. 2 shows a power MOSFET, in which a p° well 21 and a p-channel region 22 are integrally provided on one surface side of an n-type silicon substrate l that will serve as a drain region, and an n° source region 3 is further provided on the surface layer. and both source regions 3
A gate electrode 5 made of, for example, polycrystalline silicon is provided between the channel region 22 between the drain region 1 and the drain region 1 via a gate oxide Wa4. Source region 3 and p
°The well 21 has PSG insulation j1 between it and the gate electrode 5.
The source ti6, which is insulated by 9 and connected to the source terminal S, is in contact therewith, and the other side of the base +Ji1 is in contact with the drain electrode 8, which is connected to the drain terminal via the n° layer 7. When a positive voltage is applied from the gate terminal G to the source electrode 6 to the gate electrode 5 of this semiconductor element, the p-channel region 22 between the n source region 3 and the n drain region l is inverted and an n channel is generated. However, electrons are injected from the source region 3 through the channel into the drain region, thereby bringing the source electrode 1 and the drain electrode into a conductive state.

By biasing the gate ring i5 to the same potential as the source gl#IjA6 or to a negative bias, it enters a blocking state and operates as a Sino-Nang element.

In this structure, a p'' layer is provided in place of the n'' layer 7, and a genuine bill is injected from the p'' layer into the 0 layer 1 in a conductive state, resulting in conductivity modulation in the n layer 1.
It is ET.

Figure 3 ta+ - (al is the MOS F shown in Figure 2.
E 'Alternatively, this shows the conventional manufacturing process of the MOS structure of an IGBT. First, a p-square region 21 is formed on the surface layer of an n-type silicon substrate l, and then the oxide film on the surface is removed by etching. (Figure aL) Next, a gate oxide film 4 and a polycrystalline silicon layer 5 are laminated on the surface, and then patterned in a photoetching process, and using the pattern as a mask, ion implantation 1 drive is performed to form the p-6ff region 22.
(Figure b). Further, a resist It'll is patterned on the p'fiIi region 21 by a photoetching process, and using this as a mask, a thin source region 3 is formed by ion implantation (FIG. C). After this, the surface is covered with PSG layer 9.
(Figure d) and form a contact hole for the source electrode in a photo-etching process (Figure e).

[Problems to be Solved by the Invention] As described above, the conventional method requires the formation of a resist pattern in order to introduce impurities into the source region. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing an M0S type semiconductor device that eliminates the need to form this resist pattern in order to reduce the number of steps.

[Means to solve the problem]

In order to solve the above problems, the present invention provides a channel region of a second conductivity type in the surface layer of the drain region of the first conductivity type, and a gap between the channel region and the drain region in the surface layer of the channel region. A source region of a quaternary conductivity type is formed, a high impurity concentration region of a second conductivity type is formed inside the source region and a channel region, and a gate electrode is formed above the gap between the source region and the drain region. When manufacturing a MOS type semiconductor device, a source 1Etfi is provided in a part of the source region and the high impurity region through the gate ring (rabbit and !f!! edge layer). After forming a conductive type high impurity concentration region in the drain region, the surface oxide film is coated with high impurity concentration 1.
After removing only a predetermined area on the gate region and stacking the gate oxide film and the gate tpjA layer, patterning of the gate N girder and the gate oxide film thereunder is performed using the remaining @
The Ifli film is left in place, and ion implantation for forming a source region is performed using the electrode 111, gate oxide film pattern, and the residual oxide film as a mask.

[Made]

In addition to the conventional gate oxide film and gate oxide film pattern, ion implantation for forming the source region uses the oxide film left on the high impurity region formed for source electrode contact, so the resist pattern is Resist coating and photoetching steps for formation become unnecessary.

〔Example〕

FIG. 1 shows the manufacturing process of a MOS structure according to an embodiment of the present invention. Components common to those in FIG. 3 are given the same reference numerals. Figure 1 (Al) Figure 3 [After forming the p'f+jl region 21 by impurity diffusion in the same way as in al, the oxide film is not completely removed, and most of the p'' region is oxidized (11141).
Leave it. Next, in FIG. 1 fbl, p- region 2 is formed by ion implantation and driving similar to those in FIG.
After forming 2, the oxide film 41 is left as a gate oxide film and the resist as shown in FIG.
used instead of the already patterned gate oxide 11
94. Day 1' FIt pole 5 upper.

This is used as a mask for forming the n° source region 3. After this, the surface is covered with a PSG layer 9 in the same way as in Fig. 3 +d+ (Fig. C).
, Form a contact hole in the same photo-etching process as shown in Figure 3 (Figure d), and remove the remaining oxidation 1.
Since 141 is removed in this step, the state of fd+ in FIG. 1 and the state of FIG. 3 (8) are exactly the same, and the oxidized 111
! The step of leaving 41 can use the conventional oxide film removal step after forming the p'' region 21, so the number of steps is reduced by one.

〔Effect of the invention〕

According to the present invention, after the formation of a highly impurity region in contact with the source electrode, during the oxide film removal step, the oxide film left in a predetermined portion on the high concentration impurity layer is removed by ions for forming the source region. Since it is used as part of the mask during implantation, there is no need to form a resist pattern for the mask for ion implantation into the source region, and M
It has become possible to manufacture OS type semiconductor devices.

[Brief explanation of the drawing]

Fig. 1 fa1 to Fdl are cross-sectional views sequentially showing the manufacturing process of an embodiment of the present invention, Fig. 2 is a cross-sectional view of a power MOSFET manufactured based on the present invention, and Fig. 3 (al to +a+ are conventional 1 is a cross-sectional view sequentially showing the manufacturing process. 1: Si substrate, 2i: p' region 22: p-channel region, 3: n' source region 4: gate oxide film, 4 remaining oxide film, 5: gate electrode , 6; source electrode, 9: P2
O layer. To 11 people 1thx person Yamaguchi Kame 1st plan 2nd figure 3rd figure

Claims (1)

[Claims] 1) A channel region of a second conductivity type is provided in the surface layer of the drain region of the first conductivity type, and a source region of the first conductivity type is provided in the surface layer of the channel region with a gap between the drain region and the drain region.
A high impurity concentration region of the second conductivity type is formed in the channel region inside the source region, a gate electrode is formed above the gap between the source region and the drain region, and a part of the source region and the high impurity concentration region are formed. A gate electrode and a source electrode via an insulating layer are provided in the doped region. When manufacturing a semiconductor device, first a high impurity concentration region of the second conductivity type is formed as a drain region, and then a surface oxide film is formed on the high impurity concentration region. After removing only a predetermined region while leaving it, and then stacking a gate oxide film and a gate electrode layer, the gate electrode and the gate oxide film thereunder are patterned leaving the residual oxide film, and ions are implanted to form a source region. A method of manufacturing a MOS type semiconductor device, characterized in that the above step is performed using a gate electrode, a gate oxide film pattern, and the residual oxide film as a mask.