JPH0243750A - Method of identifying defect of inactivated layer and method of forming corrosion-resistant bonding pad - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION CROSS-REFERENCE TO RELATED APPLICATIONS This application is incorporated herein by reference to the following application, United States Patent Application Section 1, filed April 29, 1988, and assigned to the assignee of this application:
No. 88.294, Inventors Owen W, Hatcher, ``Corrosion Resistant Ponding Pad'' (cORROSION TOLE)
RANT BONDING PAD).

BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a method for electrically rejecting integrated circuit devices having damaged passivation layers.

2. Description of the Related Art As shown in the partial cross-sectional view of FIG. 1, in conventional integrated circuits, interconnects 12 provide electrical connections between individual elements (not shown) of the integrated circuit; bonding·
Extended areas called pads 13 extend to the edges of the integrated circuit provided. Metal lead wire 14
are attached to bonding pads 13 to provide power, signals, and other electrical interconnections to the integrated circuit. Interconnect 12 is typically formed from 90% to 100% pure aluminum, and lead wire 14 is typically formed from gold, but may also be formed from aluminum. Lead wire 14 is attached to bond pad 13 by thermocompression bonding to create bond area 15.

Interconnects 12 and bonding pads 13 are SiO
2, covered by a passivation layer 16 formed of doped SiO2, Si, N4, or a combination of layers formed of these materials. Passivation layer 1
Any defect 17 in the passivation layer 16 that exposes the underlying interconnect 12 to contaminants or corrosive agents, such as cracks, pin holes, or other attributes of the passivation layer 16, can be catastrophic in an integrated circuit. In particular, portion 12a of interconnect 12 creates a discontinuity in interconnect 12, or portion 12a of interconnect 12
oxidized and/or otherwise corroded in a manner that converts a into a non-conductive material, such as aluminum oxide or aluminum hydroxide.

In either case, the result is an integrated circuit that does not function properly because the affected interconnect 12 does not conduct electricity. Failure of an integrated circuit due to defects in the passivation layer may occur only long after the integrated circuit has been fabricated. However, it is desirable to identify potentially faulty integrated circuits during manufacture to avoid selling such devices.

Defects in passivation layer 16 are difficult, if not impossible, to detect visually, attempts at meaningful visual inspection are time consuming and expensive, and pass/fail decisions are subjective. at most, it can only detect a small number of defects. Such visual inspection requires the use of a microscope or other optical device with a limited viewing range. A magnification of at least 500x is required for meaningful inspection, and many defects cannot be detected without the aid of a scanning electron microscope. However, until now, only integrated circuits with macroscopic defects have been identified as rejected devices prior to wafer sorting and packaging steps.

Destructive testing using an acid etch followed by visual inspection has been used to test the integrity of passivation layers in completed integrated circuit devices.

These destructive tests cannot be used on an entire wafer basis because they destroy the tested device. Instead, selected devices are tested in an attempt to identify lots of defective devices.

Corrosion of bonding pads is also a problem. The aperture 18 of approximately 16 to 20 m 112 is typically 20 to 2
It is provided through a portion of the passivation layer 16 corresponding to the center of the bonding pad 13, which is 5 m112.

However, bond area 15 is only 30 to 70% of bonding pad 13 exposed by aperture 18.
It only covers that part. In this manner, a portion of each bonding pad 13 remains exposed even after leads 14 are attached thereto. In areas of aperture 18 where bond region 15 does not cover bond pad 13,
Aluminum bonding pad 13 is subject to oxidation or other corrosion.

This oxidation or corrosion turns aluminum bonding pad 13 into a non-conducting material. If oxidation of bonding pad 13 occurs in region 13b, the bonding pad 13
This creates an increased resistance between pad 13 and interconnect 12 and, in the worst case, an open circuit between bonding pad 13 and the remainder of interconnect 12.

When passivation layer 16 is doped 5i02, moisture that enters the integrated circuit package combines with the phosphorus present as a dopant in passivation layer 16 to form phosphorous acid, which reacts with the exposed aluminum. Converts aluminum to aluminum oxide or aluminum hydroxide. This phenomenon is facilitated by direct contact between the exposed portions of bonding pad 13, particularly portions 13b and passivation layer 16.

Other sources of corrosion may be associated with integrated circuit packaging materials. Typically, the package is a plastic material that may have components that cause corrosion. Additionally, other sources of corrosive materials may be present within the integrated circuit itself or may occur as a result of the fabrication or packaging process.

SUMMARY OF THE INVENTION It is therefore an object of the invention to propose a method for identifying integrated circuits with defects in the passivation layer.

It is a further object of this invention to provide a method of fabricating corrosion resistant bond pads for interconnects that includes testing the integrity of a passivation layer provided over the interconnects.

Another object of the invention is to replace the traditional inkstone sense test.
It is an object of the present invention to provide a method of electrical testing to determine whether a passivation layer is damaged.

According to the method of the present invention, conventional integrated circuits can be tested to determine if the passivation layer has any defects, and integrated circuits with corrosion resistant bonding pads can be tested to detect defects in the passivation layer. It can be manufactured by a method including steps. In particular, an integrated circuit having a corrosion-resistant bonding pad over a portion of the interconnect and a passivation layer over the remaining portion of the interconnect is tested to ensure that the passivation layer is A method for determining whether the interconnect is damaged is to expose a portion of the interconnect through an opening in the passivation layer, provide a barrier layer over the portion of the interconnect that corresponds to the opening in the passivation layer, and remove the barrier layer. A bonding layer is provided above the layer, and the integrated circuit is exposed to an etchant that etch the interconnects, such that portions of the interconnects that are below the damaged portions of the passivation layer are etched, and that this etching step removes any contact with the interconnects. and determining whether a discontinuity has occurred.

An advantage of the invention is that integrated circuits that are likely to fail due to defects in the passivation layer can be identified during fabrication.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of fabricating corrosion-resistant bonding pads and determining whether an integrated circuit has any defects in the passivation layer is described in connection with FIGS. 2A-2E and FIG. . A fourth method for detecting defects in a passivation layer of an integrated circuit device having conventional bonding pads
DESCRIPTION OF THE PREFERRED EMBODIMENTS It should be understood that the materials, thicknesses, structures, and processing parameters described with respect to preferred embodiments of the invention are exemplary and not intended to limit the scope of the invention. [The term bonding pad J refers to a single or multilayer structure that serves for electrical interconnection with interconnects and lead wires. The term "defect" as used with respect to a passivation layer refers to any structural aspect of the passivation layer that exposes the underlying layer to the atmosphere to which the exposed surface of the passivation layer is exposed. also means

A completed integrated circuit with corrosion resistant bonding pads is shown in FIGS. 2A and 2E. The integrated circuit is one of many integrated circuits that are formed simultaneously on a single wafer, so this description alternately refers to a single and multiple integrated circuits. The substrate 10 has interconnects 12 provided thereon, and as in conventional semiconductor devices, the interconnects 12 are made of aluminum or a compound of aluminum and copper and/or silicon, such as aluminum copper, aluminum silicon, aluminum copper. It can be made of silicon.

Alternatively, interconnect 12 may be formed of other materials or compounds that are electrical semiconductors and are useful in the fabrication of semiconductor devices according to techniques known in the semiconductor industry. Additionally, interconnects 12 can be formed directly on substrate 10 or on other layers disposed on substrate 10. For example, interconnect 12 may be provided on an insulating layer that separates it from other underlying interconnects (not shown), such as in a dual metallization structure.

A passivation layer 16 formed by conventional techniques is provided over the interconnect 12 and has an aperture (or opening) 18 to expose the extended bonding region 26 of the interconnect 12. A corrosion-resistant conduction barrier layer 28 is provided over the bonding region 26 of the aperture 18 of the passivation layer 16 to prevent oxidation or other corrosion of the bonding region 26 of the interconnect 12 . Examples of materials that can be used to form barrier layer 28 include:
tungsten and titanium and compounds of these materials,
or other materials in packaged integrated circuits that do not undergo significant oxidation or corrosion when exposed to phosphorous acid or other agents.

The barrier layer is made of a compound of titanium and tungsten (Titanium Gesten or Ti) having a thickness of about 1000 to 2000 nm.
W).

Barrier layer 28 protects bonding region 26 of interconnect 12 from being exposed to oxidizing or other corrosive environments.
is provided both in the entire aperture 18 and in the portion 14a of the passivation layer 14 surrounding the aperture 18. Barrier layer 28 can be formed by co-sputtering titanium and tungsten targets or by electron beam (E-beam) welding. Barrier layer interconnect 12
Make ohmic contact with. Therefore, oxidation of interconnect 12 prior to deposition of barrier layer 28 must be avoided, and if any oxidation occurs, the oxide must be removed, eg, by reverse sputtering.

A bonding layer 30, for example made of aluminum, is provided over the barrier layer 28, and the lead wires 14 are attached to the bonding layer 30 using conventional bonding techniques, such as thermocompression bonding. bonding layer 30
can also be made of gold. If bonding layer 30 is gold, it can be fabricated by common lift-off techniques. In a preferred embodiment, bonding layer 3
0 is made of 90% to 100% pure aluminum and has a thickness of approximately 1 μm. But 0°25 to 2
It can have a thickness of μm. bonding layer 30
can be provided using the same techniques used to provide barrier layer 28. Again, the barrier layer 28 and the bonding layer 3
Ohmic contact must be provided between the

Another property of the material chosen for barrier layer 28 is that it must not be penetrated by the material of bonding layer 30 during subsequent fabrication steps or at the temperatures experienced in integrated circuit operation. .

This structure prevents corrosion of the bonding area 26 of the interconnect 12 so that even if the bonding pad 30 corrodes, the bonding pad 3 underlying the bond 18
The zero portion is protected from corrosion, thereby preventing or substantially delaying increased resistance and/or open circuits between lead wire 14 and interconnect 12.

Fabricate corrosion resistant bonding pads and passivation layer 1
A method for detecting defects 6 is described with respect to FIGS. 2B-2E. First, expanded bonding area 2
An interconnect 12 having a passivation layer 16 is provided on the substrate 10, which may be a combination of several different layers, as explained above. An aperture 18 is provided over the interconnect 12 and drilled into the passivation layer 16 .

Barrier layer 28 and bonding layer 30 are then produced as successive layers, as shown in FIG. 2C. A masking layer is applied to bonding layer 30 and patterned using standard photolithographic techniques to leave mask 32 in the form of bonding pads.

As shown in FIG. 2D, a mask 32 is used to define the shape of the bonding pad while the unwanted portions of the activation layer 28 and bonding layer 30 are removed. At this point in the process, with mask 32 in place, the integrated circuit is exposed to an etchant that penetrates defects in passivation layer 16 and etches the material forming interconnects 12. If there are any defects in passivation layer 16, the etchant will corrode interconnect 12 thereby creating a discontinuity in interconnect 12. Mask 32 is then removed.

When an integrated circuit is subjected to wafer sorting, including electrical inspection, the integrated circuit will fail inspection if any of the interconnects 12 do not become conductive due to the presence of discontinuities created during the etching step. Even if interconnect 12 is nonconductive for other reasons, an integrated circuit subjected to the process of the present invention will fail test if passivation layer 16 is defective. Integrated circuits that pass the wafer sorting test are sent for further processing, including sorting the individual die on the wafer, packaging, and bonding lead wires 20. Importantly, all devices on the wafer can be inspected without damaging those devices that do not have defects in the passivation layer 6.

The primary etchant used to detect defects in passivation layer 30 may be phosphorous acid.

Phosphorous acid is the primary etchant and comprises about 90°6 of the etching solution, and nitric acid and/or acidic acids can be added to the etching solution. Other wet etchants and etching methods other than wet etching can be used. For example, isotropic plasma etching can be used. Of course, any etching method that performs side etching can be used. Side etching etches the entire width of interconnect 12 even though defects in passivation layer 16 do not exceed the entire width of interconnect 12.

However, it is noted that the entire width of phase n-connection 12 need not be etched. Partial etching of interconnect 12 can be detected by measuring the increased resistance along interconnect 12 or by using other detection means such as x-rays.

The etchant can be heated to speed up the etching process and promote penetration of cracks and other defects. Temperatures of 40 to 50°C are believed to be useful for this purpose, although temperatures of 70 to 80°C or higher may be used.

Etching time depends on temperature and interconnect width and thickness. Generally, the etch time must be long enough so that the entire width of interconnect 12 is etched.

Therefore, a passivation layer 16 is provided on one side of the interconnect 12.
If a defect exists, a discontinuity in interconnect 12 will still occur. Thickness 0.5 to 1.5 μm and width 5 to 75 μm
For .mu.m interconnects, an etchant temperature of 40 to 50.degree. C. requires an etch time of 10 to 15 minutes, and an etchant temperature of 70 to 80.degree. C. requires an etch time of less than 5 minutes.

An alternative embodiment of a corrosion resistant bonding pad is described with respect to FIG. In an alternative embodiment bonding layer 3
0' has a smaller area than barrier layer 28. For example, barrier layer 28 and bonding layer 30' are square;
If the barrier layer 28 has dimensions X and y, respectively, the area X
2 is larger than the area y2 of the bonding layer 30'. The purpose of reducing the area of bonding layer 30' with respect to the area of barrier layer 28 is to increase the physical separation between aluminum bonding layer 30' and passivation layer 16, thereby reducing the phosphorus dopant ions in the passivation layer. This reduces or eliminates the possibility that the phosphorous acid formed from the bonding layer 30' will react with the aluminum of the bonding layer 30'.

The reduced size of bonding layer 30' can be achieved in two ways. Barrier layer 2 as mentioned above
8 and the bonding layer 30' are produced as a patterned continuous layer by standard photolithographic techniques. If one mask is used to etch the patterns of both barrier layer 28 and bonding layer 30', the integrated circuit is first etched with aluminum bonding layer 30'.
and then exposed to an etchant to etch the barrier layer 28.
is exposed to an etchant that etches the material, followed by a second etch using an etchant for aluminum to cause etching of the sides of bonding layer 30'. In this method, the etchant for aluminum must be a selective etchant that does not etch the material of barrier layer 28. Etchant selectivity can be obtained by selecting appropriate etchants or by selecting materials for barrier layer 28 and bonding layer 30' that are not affected by the same etchant.

If separate masks are used to etch the patterns of barrier layer 28 and bonding layer 30', it is necessary to protect barrier layer 28 and bonding layer 30 during the etching process in order to provide the desired differences in the area of barrier layer 28. The area of the mask is selected. In both techniques used in the second embodiment of the invention, the etchant used to etch the sides of aluminum bonding layer 30 removes barrier layer 28 from most of passivation layer 16. After removal, passivation layer 16 and the portions of interconnect 12 underlying the defects in passivation layer 16 are exposed to an etchant during lateral etching of bonding layer 30.

The method of the present invention applies any portion of the integrated circuit intentionally exposed through passivation layer 16 (e.g., conventional bonding pad)
This can also be done by masking. Fourth
The figure shows an integrated circuit having conventional bonding pads 13 with a mask 34 disposed over the bonding pads 13 so that the integrated circuit can be exposed to an etchant. The etchant creates discontinuities 36 in portions of interconnect 12 underlying defects in passivation layer 16. In this manner, integrated circuits having defects in the passivation layer 16 can be sorted out during the wafer 11 sorting process.

Any method known as a method of wafer exploration,
That is, methods of functional testing before the integrated circuit is packaged can also be used to determine whether the etching step of the present invention has created a discontinuity in interconnect 12. Examples of wafer exploration methods are electrical exploration using mechanical probing to physically connect each bonding pad, and various methods in which current is induced in the interconnects by illuminating the integrated circuit with an electron beam or laser beam. Including types of beam exploration. Additionally, interconnect discontinuities can be detected using x-rays.

The many features and advantages of the method of fabricating corrosion-resistant bonding pads and simultaneously detecting passivation layer defects in accordance with the present invention will be apparent to those skilled in the art. It is therefore intended that the following claims cover all modifications and equivalents falling within the scope of this invention.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a conventional bonding pad. FIG. 2A is a top view of a corrosion resistant bonding pad according to the present invention. 2B to 2E are cross-sectional views for explaining the present invention in detail, and FIG. 2E is a cross-sectional view taken along the line E-E' in FIG. 2A.
This is a cross section taken along. FIG. 3 is a cross-sectional view of an alternative embodiment of a corrosion resistant bonding pad according to the present invention. FIG. 4 is a cross-sectional view illustrating the present invention as used in an integrated circuit having conventional bonding pads. In the figure, 10 is a substrate, 12 is an interconnection,
13 is a bonding pad, 14 is a lead wire, 1
5 is a bond region, 16 is a passivation layer, 18 is an aperture, 26 is a bonding region, 28 is a barrier layer, 30 is a bonding layer, and 34 is a mask. Patent applicant: Advanced Micro-DμFIG,
-2C FIG, -1 FIG, -2A FIG, -2E

Claims (18)

[Claims] (1) A method for identifying defects in a passivation layer disposed over an interconnect, the method comprising: (a) providing a mask over portions of an integrated circuit intentionally exposed by the passivation layer; (b) exposing the passivation layer to an etchant to etch portions of the interconnect underlying the damaged portion of the passivation layer; and (c) removing the interconnect after said step (b). and inspecting the interconnect to detect any etching of the interconnect. 2. The method of claim 1, wherein step (c) includes wafer classification. 3. The method of claim 1, wherein step (a) includes masking bonding pads overlying interconnects. 4. The method of claim 1, wherein step (c) also includes electrically testing the interconnects to detect any discontinuities in the interconnects. (5) A method of testing to identify integrated circuits having defects in a passivation layer disposed over an interconnect, the method comprising: (a) exposing a portion of the interconnect through an aperture in the passivation layer; (b) providing a corrosion resistant bonding pad over the portion of the interconnect exposed by the aperture in the passivation layer; and (c) exposing the passivation layer to an etchant to passivate the passivation layer. (d) inspecting the interconnect to detect discontinuities in the interconnect after step (c); Method. (6) The method of claim 5, wherein (c) includes wafer classification. 7. The method of claim 5, wherein step (a) includes masking bonding pads overlying interconnects. (8) The method of claim 5, wherein step (c) includes electrically testing interconnects. (9) Inspecting integrated circuits having corrosion-resistant bonding pads over interconnects and passivation layers over interconnects to determine whether the passivation layers are damaged. (a) exposing a portion of the interconnect through an opening in the passivation layer; and (b) depositing a barrier layer over the portion of the interconnect corresponding to the opening in the passivation layer. (c) providing a bonding layer over the barrier layer; and (d) an etchant for etching the interconnect such that portions of the interconnect underlying the damaged portion of the passivation layer are etched. (e) determining whether step (d) resulted in a discontinuity in the interconnect. 10. The method of claim 9, wherein step (b) further comprises providing a barrier layer over the portion of the passivation layer surrounding the opening in the passivation layer. 11. The method of claim 10, wherein step (b) includes providing a titanium and tungsten barrier layer. 12. The method of claim 11, wherein step (c) includes providing an aluminum bonding layer. 13. The method of claim 9, wherein step (d) includes laterally etching the bonding layer to reduce the area of the bonding layer. 14. The method of claim 9, wherein step (c) includes wafer classification. 15. Claim 9, wherein step (a) includes masking bonding pads disposed over the interconnect.
The method described in. 16. The method of claim 9, wherein step (c) includes electrically testing interconnects. (17) A method for fabricating corrosion-resistant bonding pads for interconnects formed on a substrate and testing the integrity of a passivation layer disposed over the interconnects, the method comprising: (a) (b) providing a barrier layer over the portion of the interconnect exposed through the aperture of the passivation layer; and (c) exposing the portion of the interconnect through the aperture of the passivation layer. (d) masking the barrier layer and the bonding layer; and (e) exposing the passivation layer to an etchant that etches the interconnects after masking the barrier layer and the bonding layer. (f) inspecting the interconnect to detect the interconnect discontinuity created by step (e). (18) A method of fabricating corrosion-resistant bonding pads for interconnects formed on a substrate and electrically testing the integrity of a passivation layer disposed over the interconnects, comprising: (a) exposing a portion of the interconnect through the aperture in the passivation layer; and (b) over the portion of the interconnect exposed through the aperture in the passivation layer and over the passivation layer. (c) providing a bonding layer over the barrier layer; and (d) forming an aperture in the passivation layer and a selected portion of the passivation layer surrounding the aperture in the passivation layer. providing a mask over corresponding portions of the barrier layer and bonding layer; (e) removing portions of the barrier layer and bonding layer other than portions of the barrier layer and bonding layer underlying the mask; and (f) ) exposing the passivation layer to an etchant to etch the interconnect; and (g) applying a current to the interconnect to detect the interconnect discontinuity caused by step (f). Method.