JPH0243795A - Resistance adjustment of thick film hybrid integrated circuit - Google Patents
Resistance adjustment of thick film hybrid integrated circuitInfo
- Publication number
- JPH0243795A JPH0243795A JP19373088A JP19373088A JPH0243795A JP H0243795 A JPH0243795 A JP H0243795A JP 19373088 A JP19373088 A JP 19373088A JP 19373088 A JP19373088 A JP 19373088A JP H0243795 A JPH0243795 A JP H0243795A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- printed
- chip resistor
- resistance value
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 abstract description 8
- 238000009966 trimming Methods 0.000 description 13
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】 Ａ、産業上の利用分野 この発明は厚膜混成集積回路の抵抗調整法に関する。[Detailed description of the invention] A. Industrial application field The present invention relates to a method for adjusting resistance of thick film hybrid integrated circuits.
Ｂ１発明の概要
この発明は、厚膜混成集積回路の印刷抵抗（厚膜抵抗）
が接続されるランドを端部に有する印刷配線の前記ラン
ド近くにチップ抵抗接続用のランドを設け、前記印刷抵
抗の値が所定値より大きい場合、これに並列接続する抵
抗調整用のチップ抵抗との合成抵抗値が前記所定値と略
等しくなるか、或は小さく且つ前記所定値に近くなるよ
うなチップ抵抗を標準シリーズ中から選んで、前記合成
抵抗値が前記所定値の許容範囲内に入る場合は前記チッ
プ抵抗を前記チップ抵抗接続用ランドに接続し、又前記
合成抵抗値が前記所定値の許容範囲より小さくなる場合
は前記印刷抵抗をトリミングして前記合成抵抗値が前記
許容範囲内に入るようにした後に前記チップ抵抗を前記
チップ抵抗接続用ランドに接続して印刷抵抗の抵抗値を
調整するものである。B1 Summary of the Invention This invention relates to a printed resistor (thick film resistor) of a thick film hybrid integrated circuit.
A land for connecting a chip resistor is provided near the land of the printed wiring which has a land at the end to which the printed wiring is connected, and when the value of the printed resistor is larger than a predetermined value, a chip resistor for resistance adjustment is connected in parallel to the land. Select a chip resistor from a standard series whose combined resistance value is approximately equal to the predetermined value, or is small and close to the predetermined value, and the combined resistance value falls within the allowable range of the predetermined value. If so, the chip resistor is connected to the chip resistor connection land, and if the combined resistance value becomes smaller than the allowable range of the predetermined value, the printed resistor is trimmed so that the combined resistance value falls within the allowable range. After the printed resistor is inserted, the chip resistor is connected to the chip resistor connecting land to adjust the resistance value of the printed resistor.
Ｃ１従来の技術
厚膜混成集積回路の印刷抵抗（厚膜抵抗）はその抵抗値
をトリミングで調整するため、通常は所定の抵抗値より
４０〜８０％小さくなるように作られており、トリミン
グにより抵抗値を増加させて所定の抵抗値となるように
している。C1 Conventional technology Printed resistors (thick film resistors) of thick film hybrid integrated circuits have their resistance values adjusted by trimming, so they are usually made to be 40 to 80% smaller than the predetermined resistance value. The resistance value is increased to a predetermined resistance value.
Ｄ８発明が解決しようとする課題
しかしトリミングによっては抵抗値を大きくすることは
できるが小さくすることはできない。このため従来はト
リミングにより大きくなり過ぎた抵抗値を小さくするの
にジャンパーを用いて印刷抵抗の一部を短絡したり、別
の印刷抵抗を回路上平行となるように設けて並列接続す
る方法をとりている。しかし、これらの方法では接続と
いう作業を必要とし、製造工程の中でノ＼ンダ付は作業
が入り又ハンダ付後トリミングにより抵抗値を調整しな
ければならないなど工程に影響を与える。又、回路の設
計時点でも、前記短絡のためのランドを印刷抵抗の側方
に設けたり、面一並列接続する抵抗を側方に平行に設け
るためのスペースが必要となり、回路設計上著しく不利
となっていた。D8 Problems to be Solved by the Invention However, although the resistance value can be increased by trimming, it cannot be decreased. For this reason, conventional methods have been used to reduce the resistance value that has become too large due to trimming by shorting part of the printed resistor using a jumper, or by connecting another printed resistor in parallel on the circuit. I'm taking it. However, these methods require a connection operation, and the soldering process involves additional work during the manufacturing process, and the resistance value must be adjusted by trimming after soldering, which affects the process. Furthermore, at the time of designing the circuit, space is required to provide lands for the short circuit on the sides of the printed resistors, or to provide parallel parallel connections on the sides, which is a significant disadvantage in circuit design. It had become.
この発明は面一従来の問題に鑑みてなされたらので、印
刷抵抗の側方にスペースを設けることなく、しかも標準
シリーズ中から選んだチップ抵抗を用いて抵抗調整がな
しうろ厚膜混成集積回路の抵抗調整法を提供することを
目的とする。Since this invention was made in view of the existing problems, it is possible to create a thick-film hybrid integrated circuit without providing any space on the side of the printed resistor, and with resistance adjustment using chip resistors selected from the standard series. The purpose is to provide a resistance adjustment method.
Ｅ１課題を解決するための手段
この発明は、厚膜混成集積回路の印刷抵抗が接続されろ
ランドを端部に有する印刷配線の前記ランド近くにチッ
プ抵抗接続用ランドを設け、前記印刷抵抗の値が所定値
より大きい場合、これに並列接続する抵抗調整用のチッ
プ抵抗との合成抵抗値が前記所定値と略等しくなるか、
或は小さく且つ前記所定値に近くなるようなチップ抵抗
を標準シリーズの中から選び、前記合成抵抗値が前記所
定値の許容範囲となる場合は前記チップ抵抗を前記チッ
プ抵抗接続用のランドに接続し、又前記合成抵抗値が前
記所定値の許容範囲より小さくなる場合は前記印刷抵抗
をトリミングして前記合成抵抗値が前記許容範囲内に入
るようにした後前記チップ抵抗を前記チップ抵抗接続用
ランドに接続して印刷抵抗の抵抗値を調整することを特
徴とずろものである。E1 Means for Solving Problems This invention provides a land for connecting a chip resistor near the land of a printed wiring having a land at an end to which a printed resistor of a thick film hybrid integrated circuit is connected, and is larger than the predetermined value, the combined resistance value with the chip resistor for resistance adjustment connected in parallel with it is approximately equal to the predetermined value, or
Alternatively, select a chip resistor from a standard series that is small and close to the predetermined value, and if the combined resistance value falls within the allowable range of the predetermined value, connect the chip resistor to the land for connecting the chip resistor. However, if the combined resistance value becomes smaller than the allowable range of the predetermined value, the printed resistor is trimmed so that the combined resistance value falls within the allowable range, and then the chip resistor is connected to the chip resistor. It is unique in that it connects to the land to adjust the resistance value of the printed resistor.
Ｆ１作用
したがってこの発明によれば、調整用のチップ抵抗を、
印刷抵抗が接続されるランドを端部に有する印刷配線の
前記ランド近くに設けたデツプ接続用のランドに接続し
、印刷抵抗の上部の重なり合うように設けることができ
るので、調整用の低抗を設けるためのスペースを必要と
しない。又調整用の抵抗として標準シリーズの中から選
んだチップ抵抗を用いているので、チップ抵抗を接続し
た後印刷抵抗をトリミングする必要がなくなる。F1 action Therefore, according to the present invention, the chip resistor for adjustment is
The land to which the printed resistor is connected can be connected to the land for deep connection provided near the land of the printed wiring at the end, and can be provided so as to overlap the upper part of the printed resistor, so that the low resistance for adjustment can be made. No space required for installation. Furthermore, since a chip resistor selected from the standard series is used as the adjustment resistor, there is no need to trim the printed resistor after connecting the chip resistor.
Ｇ、実施例
第１図、第２図において、１．ｌ’は印刷配線、２．２
′は印刷配線！、ビの端部に一体に設けられた印刷抵抗
用ランド、３は印刷抵抗用ランド２．２′間に設けられ
印刷抵抗、４．４′は印刷配線１，１′の前記印刷抵抗
用ランド２．２′の近くに設けられたチップ抵抗用ラン
ド、５はチップ抵抗用ランド４．４′間に前記印刷配線
の上部に市なり合うように設けられた調整用のチップ抵
抗である。G. Example In FIGS. 1 and 2, 1. l' is printed wiring, 2.2
’ is printed wiring! , 3 is the printed resistance land provided between the printed resistance lands 2 and 2', and 4.4' is the printed resistance land of the printed wiring 1 and 1'. A chip resistor land 2.2' is provided near the chip resistor land, and 5 is an adjustment chip resistor provided between the chip resistor lands 4 and 4' above the printed wiring so as to be aligned with each other.
先づ印刷配線１．１′に第１図のように印刷抵抗３が印
刷される。この印刷抵抗３はトリミングされ所定の抵抗
値Ｒとすべきところ、抵抗値Ｒの許容範囲を超える抵抗
値Ｒ１になったものとする。First, a printed resistor 3 is printed on the printed wiring 1.1' as shown in FIG. This printed resistor 3 should be trimmed to a predetermined resistance value R, but it is assumed that the resistance value R1 exceeds the tolerance range of the resistance value R.
第３図はその等価回路である。FIG. 3 shows its equivalent circuit.
そこで、チップ抵抗５を第２図のように接続して印刷抵
抗３と並列接続した場合、その合成抵抗が前記Ｒの値に
近いか、或は若干小さくなるような抵抗値Ｒ２を有する
チップ抵抗を標準シリーズより選択して印刷抵抗３とチ
ップ抵抗５との合成抵抗Ｒｏ即ち、ｒｔ ｏ ＝ ＲＩ
−Ｒｔ／ （Ｒｌ＋ Ｒ２）が所定の抵抗値Ｒの許容範
囲内に入っている場合は抵抗値Ｒ２のチップ抵抗を第２
図のように接続する。第４図はその等価回路である。又
、上記合成抵抗Ｒｏが所定の抵抗値Ｒの許容範囲より小
さい場合は再び印刷抵抗３をトリミングしてその抵抗値
【しを大きくしてチップ抵抗５との合成抵抗Ｒ１が所定
の抵抗値Ｒの許容範囲に入るようにしてから第２図のよ
うにチップ抵抗５を接続するものである。尚、印刷され
た印刷抵抗はトリミング後絶縁コーテングされるのが通
常の工程であるが、チップ抵抗をさらに重さねるときは
、トリミング後、絶縁コーテングした後にチップ抵抗を
印刷抵抗に重ねて接続されることは言うまでもないこと
である。Therefore, when the chip resistor 5 is connected in parallel with the printed resistor 3 as shown in Fig. 2, the chip resistor has a resistance value R2 such that the combined resistance is close to or slightly smaller than the value of R. is selected from the standard series, and the combined resistance Ro of the printed resistor 3 and chip resistor 5 is determined, that is, rto = RI
-Rt/ (Rl+R2) is within the tolerance range of the predetermined resistance value R, the chip resistor with the resistance value R2 is used as the second chip resistor.
Connect as shown. FIG. 4 shows its equivalent circuit. If the combined resistance Ro is smaller than the allowable range of the predetermined resistance value R, the printed resistor 3 is trimmed again and its resistance value is increased so that the combined resistance R1 with the chip resistor 5 becomes the predetermined resistance value R. The chip resistor 5 is then connected as shown in FIG. Note that the normal process for printed resistors is to apply an insulating coating after trimming, but when stacking chip resistors, the chip resistor is layered on top of the printed resistor after trimming and insulating coating is applied. It goes without saying that this is true.
＋（、発明の詳細
な説明したこの発明にあっては、次に述べるような効果
を奏するものである。+(, This invention, which has been described in detail, has the following effects.
（＋）印刷抵抗の抵抗値が所定の抵抗値より初めから大
きかったとき、或はトリミングの失敗などで所定の抵抗
値より大きくなったとき、印刷抵抗と並列にチップ抵抗
を実装することで簡単に所定の抵抗値に調整できる。(+) When the resistance value of the printed resistor is higher than the specified resistance value from the beginning, or when it becomes higher than the specified resistance value due to a failure in trimming, etc., it can be easily solved by mounting a chip resistor in parallel with the printed resistor. The resistance value can be adjusted to a specified value.
（２）チップ抵抗を用いることができ、しかも標準シリ
ーズのものから広範囲に容易に選択して使用することが
できる。(2) Chip resistors can be used, and moreover, they can be easily selected from a wide range of standard series.
（３）トリミングにより抵抗値が大きくなってしまった
印刷抵抗を再トリミングすることにより、チップ抵抗に
よる調整を更に精度よく所定の抵抗値に合わせることが
できる。(3) By re-trimming the printed resistor whose resistance value has increased due to trimming, the adjustment by the chip resistor can be adjusted to a predetermined resistance value with higher precision.
（４）前記再トリミングはチップ抵抗値を予め設定する
ことにより、慣用されているトリミング・プログラムの
中で自動的に行うことができるので、再トリミングとい
うよりトリミング失敗時の継続したトリミングとに行う
ことができる。(4) The above-mentioned re-trimming can be performed automatically in a commonly used trimming program by setting the chip resistance value in advance, so it is performed not as re-trimming but as continuous trimming when trimming fails. be able to.
（５）チップ抵抗を接続した場合チップ抵抗が印刷抵抗
の上部に重なるようになっているので、従来のジャンパ
ーを用いたもの或は別の印刷抵抗を用いるもののように
、側方にスペースを必要としたり、又製造工程の中で短
絡する工程、又は接続する工程が不要となる。(5) When connecting a chip resistor, the chip resistor overlaps the top of the printed resistor, so it does not require space on the side, unlike those using conventional jumpers or other printed resistors. In addition, there is no need for a short-circuiting or connecting process in the manufacturing process.
第１図はこの発明の実施例を示す印刷抵抗配線の平面図
、第２図は同じくチップ抵抗を接続した印刷配線の平面
図、第３図及び第４図は第１図及び第２図の夫々等価回
路図である。
ｌ、ド・・・印刷配線、２．２′・・・印刷抵抗用ラン
ド、３・・・印刷抵抗、４．４′・・・チップ抵抗用ラ
ンド、５・・・チップ抵抗。
第１
第３図
第２図
第４図FIG. 1 is a plan view of a printed resistance wiring showing an embodiment of the present invention, FIG. 2 is a plan view of a printed wiring connected with a chip resistor, and FIGS. 3 and 4 are the same as those shown in FIGS. They are equivalent circuit diagrams. l, Do...printed wiring, 2.2'...printed resistance land, 3...printed resistance, 4.4'...chip resistance land, 5...chip resistance. 1 Figure 3 Figure 2 Figure 4
Claims (1)
を端部に有する印刷配線の前記ランド近くにチップ抵抗
接続用のランドを設け、前記印刷抵抗の値が所定値より
大きい場合、これに並列接続する抵抗調節用のチップ抵
抗との合成抵抗値が前記所定値と略等しくなるか、或は
小さく且つ前記所定値に近くなるようなチップ抵抗を標
準シリーズの中から選び、前記合成抵抗値が前記所定値
の許容範囲となる場合は前記チップ抵抗を前記チップ抵
抗接続用ランドに接続し、又前記合成抵抗値が前記所定
値の許容範囲より小さくなる場合は前記印刷抵抗をトリ
ミングして前記合成抵抗値が前記許容範囲内に入るよう
にした後前記チップ抵抗を前記チップ抵抗接続用ランド
に接続して印刷抵抗の抵抗値を調整することを特徴とし
た厚膜混成集積回路の抵抗調整法。(1) A land for connecting a chip resistor is provided near the land of a printed wiring having a land at the end to which a printed resistor of a thick film hybrid integrated circuit is connected, and when the value of the printed resistor is larger than a predetermined value, this Select a chip resistor from the standard series whose combined resistance value with a chip resistor for resistance adjustment connected in parallel with the above-mentioned predetermined value is approximately equal to the above-mentioned predetermined value, or is small and close to the above-mentioned predetermined value. If the value falls within the permissible range of the predetermined value, connect the chip resistor to the chip resistor connection land, and if the combined resistance value becomes smaller than the permissible range of the predetermined value, trim the printed resistor. Resistance adjustment of a thick film hybrid integrated circuit, characterized in that the resistance value of the printed resistor is adjusted by connecting the chip resistor to the chip resistor connection land after the combined resistance value is within the tolerance range. Law.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19373088A JPH0243795A (en) | 1988-08-03 | 1988-08-03 | Resistance adjustment of thick film hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19373088A JPH0243795A (en) | 1988-08-03 | 1988-08-03 | Resistance adjustment of thick film hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0243795A true JPH0243795A (en) | 1990-02-14 |
Family
ID=16312854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19373088A Pending JPH0243795A (en) | 1988-08-03 | 1988-08-03 | Resistance adjustment of thick film hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0243795A (en) |
-
1988
- 1988-08-03 JP JP19373088A patent/JPH0243795A/en active Pending
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