JPH0243852A - Code error detection circuit - Google Patents

Abstract

PURPOSE:To grasp number of code errors accurately and to monitor the communication by using a mask pulse with a prescribed length so as to discriminate a detection signal corresponding to the code rule violation given by intention in the code and eliminating the said code. CONSTITUTION:When a violation detection means 101 detects the code rule violation of an input signal, a mask pulse generating means 102 generates a mask pulse with a prescribed length based on the detection signal. A discrimination means 103 discriminates whether or not the detection signal corresponds to the code rule violation given by intension based on the detection signal by the violation detection means 101 and the output state of the mask pulse of the mask pulse generating means 102. Since the detection signal representing the code rule violation given by intension is discriminated in this way, it is not outputted as a code error and the code error of the signal is detected accurately.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Example ■, Correspondence between the Example and FIG. 1 H0 Configuration of Example (1) Overall Configuration (ii) Configuration of Mask Pulse Generation Circuit ■, Operation of Example ■, Summary of Example ■0 Variations of the Invention Effects of the Invention [Summary] Bipolar encoded communication Regarding a code error detection circuit that monitors code errors, the purpose of the code error detection circuit is to detect code errors accurately. mask pulse generation means for generating a mask pulse of a predetermined length based on the mask pulse generation means; and based on the output state of the mask pulse generation means, it is determined whether or not the coding rule violation detected by the violation detection means is a code error in the signal. and discriminating means for discriminating, and is configured to detect a code error in a signal.

(Field of Industrial Application) The present invention is applicable to bipolar encoding systems, such as BSZ
Regarding code error detection circuits that monitor communications encoded by encoding methods that intentionally apply codes that violate coding rules to predetermined data, such as the S method and the B6ZS method, The present invention relates to a code error detection circuit that does not detect code rule violations.

[Prior Art] Data to be communicated in digital communication is encoded to be suitable for transmission over a communication line and then transmitted. One of these encoding methods is a bipolar encoding method, in which adjacent "1 degrees" in the data to be communicated are indicated by alternately assigning codes of different polarities.

Such codes of different polarity will be referred to as bipolar bits (B bits).

FIG. 6 is an explanatory diagram of data encoded by the bipolar encoding method.

For example, the code indicating the 8-bit data ladder “10011010’” is “”BOOBB O” as shown in ■ in Figure 6.
BO”.

As mentioned above, the data to be communicated is encoded so that pulses of the same polarity do not continue, so the coding rule violation detection circuit on the receiving side detects bits of the same polarity as shown in (■) in Figure 6. When received continuously, it is detected as a code error caused by noise in the transmission path.

Such a violation of the coding rule is called a bipolar violation, and the bit that violates the coding rule is called a violation bit (V
We will call it bit.

A terminal device that relays and monitors communications through a communication line includes a code rule violation detection circuit that detects code errors as described above, and a code rule violation detection circuit that detects code rule violations detected by this code rule violation detection circuit for a certain period of time T. An error determination section is provided that accumulates the number of violations (violation rate) and determines, based on the number (violation rate), whether or not there is a problem in continuing communication.

The error determination unit determines that the violation rate is a predetermined number Rν.
If it exceeds this, it is determined that an abnormality has occurred in the communication line or the terminal equipment and that the input signal being input to the terminal equipment is incorrect, and an alarm is issued to subsequent equipment such as the decoding unit.

After outputting this alarm, the error determination unit further measures the violation rate a predetermined number of times, and if the result is always less than the predetermined number Rv, it determines that the input signal is correct and resumes input signal processing. let

By the way, some bipolar encoding methods, such as the BBZS method and B6ZS method, violate the coding rules in response to consecutive "'O°" bits included in the data when encoding communication data. There is a method of outputting a predetermined code that intentionally includes a violation bit (V bit).

For example, an encoding device based on the BBZS system outputs "'0OOVBOVB'" as shown in ■ in Fig. 6 in response to 8 consecutive bits of "0" in the data. When the violation detection circuit receives this communication data, it does not detect the high error pit included in the communication data as a code error, but detects 8 consecutive bits of “O”.
o”.

On the other hand, if the communication data indicating 8 consecutive bits of "0" (see ■ in Figure 6) is transformed and transmitted as shown in ■ in Figure 6, then as shown in ■ in Figure 6, Original sign error (
In addition to 1 bit), two intentional violation focus points are also detected as code errors.

[Problems to be Solved by the Invention] By the way, in the conventional coding rule violation detection circuit described above, all coding rule violations contained in communication data are detected as code errors due to noise, etc. There is a problem in that a larger number of code errors than the number of code errors are detected, making it impossible to accurately determine the number of code errors.

In this way, if the code violation detection circuit cannot accurately grasp the number of code errors and detects a larger number of code errors than the actual number,
If the tolerance range for code errors in terminal equipment is set to a small value in order to meet the demand for improved communication quality, it is possible that the error determination unit will output alarms frequently and communication processing will be temporarily halted. It will be done.

Furthermore, when setting the allowable range of code errors to be small, the time T for accumulating code errors is set longer than before. For this reason, the time required for the error determination section to determine whether the input signal is truly abnormal becomes longer, and the time during which the terminal equipment is temporarily stopped becomes longer.

The present invention was created in view of these points, and provides a code error detection circuit that accurately detects code errors without detecting intentional violation pits as code errors. It is intended to.

[Means to solve the problem]

FIG. 1 is a principle block diagram of a code error detection circuit according to the present invention.

In the figure, violation detection means 101 detects a violation of the coding rule in a bipolar encoded input signal.

The mask pulse generating means 102 generates a mask pulse of a predetermined length based on the detection signal of the violation detecting means 101.

The determining means 103 determines whether or not the code rule violation detected by the violation detecting means 101 is a code error in the signal, based on the output state of the mask pulse generating means 1.about.2.

[For production]

When the violation detection means 101 detects a violation of the sign rule in the input signal, the mask pulse generation means 102 generates a mask pulse of a predetermined length based on the detection signal.

The determining means 103 determines whether the detection signal corresponds to a violation of the code rule intentionally entered, based on the detection signal from the violation detecting means 101 and the output state of the mask pulse from the mask pulse generating means 102.

In the present invention, since a detection signal indicating a violation of the coding rule that has been intentionally inserted is determined, this is not outputted as a code error, and a code error in a signal can be accurately detected.

I, and 1 Here, the correspondence between the embodiments of the present invention and FIG. 1 will be shown.

The violation detection means 101 corresponds to the code rule violation detection circuit 201.

The mask pulse generation means 102 corresponds to the mask pulse generation circuit 210.

The determining means 103 corresponds to the OR gate 203.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of a communication monitoring section using a code error detection circuit in an embodiment of the present invention.

In FIG. 2, the communication monitoring unit using the code error detection circuit in the embodiment includes a code rule violation detection circuit 201 that detects pulses (violation pits) that violate code rules from input bipolar signals. 3 of the clock signal based on the detection signal of the coding rule violation detection circuit 201.
A mask pulse generation circuit 210 that generates a mask pulse with a period length, and a detection signal and mask pulse generation circuit 21
Error determination that measures the violation rate based on the OR gate 203 that ORs the mask pulses output by 0 and the error detection signal that is the output of the OR gate 203, and outputs an alarm based on the result. Part 24
0.

The error determination unit 240 includes a counter 242 that accumulates error detection signals, a timer 241 that limits the accumulation time of error detection signals by the counter 242 to a predetermined time T, and a communication line based on the violation rate accumulated in the counter 242. and a determination section 243 that determines whether or not there is an abnormality.

Here, it is assumed that the human input signal is input in synchronization with the clock signal.

(ii Mask Pulse Generation) FIG. 3 is a configuration diagram of the mask pulse generation circuit 210 in the embodiment shown in FIG. 2.

In the figure, the mask pulse generation circuit 210 includes an OR game) 211 that ORs the clock signal and the detection signal of the sign rule violation detection circuit 201, and NAND games) 214a and 214b forming a launch circuit. gate 21
a flip-flop 212 that uses the output of 1 as a clock (CK) input and outputs a set input signal of the launch circuit;
An inverter 213 that inverts the output of the Nant gate 214a and clears the flip-flop 212, and three flip-flops 215a and 215 that function as timers.
b, 215c.

The output terminal d of the flip-flop 212 is a NAND game-1-
It is connected to one of the input terminals of 214b, and the power supply voltage is input to the input terminal, so that it is always in the "V" state.

Further, the other input terminal of the Nante gate 214b is connected to the output terminal of the Nante gate 214a and the input side of the impark 213, and the output terminal of the Nante gate 214b is connected to the flip-flop 215 of the Nante gate 214a.
It is connected to one of the clear (CL) terminal and input terminal of a, 215b, and 215C. The output terminal d of the flip-flop 215c is connected to the other input terminal of the Nant gate 214a.

Flip flop o Tsubu 215a 215b 215C
A clock signal is inputted to each clock (CK) terminal of the flip-flop 2I5a, and a power supply voltage is inputted to the input terminal of the flip-flop 2I5a.

The output terminal Q of the flip-flop 215a is connected to the input terminal of the flip-flop 215b, and the output terminal Q of the flip-flop 215b is connected to the input terminal of the flip-flop 215C.

Figures 4 and 5 are timing diagrams illustrating the operation of the embodiment shown in Figure 2.

The operation of the embodiment will be described below with reference to FIGS. 2 to 5.

■ in Figure 4 shows that a signal encoded with 8 consecutive bits of ``0'' using the B8ZS method (see ■ in Figure 4) has a pulse of polarity ``+'' on the 0th bit due to noise during transmission. This shows the received signal when it is transmitted mixed with

When such a signal is inputted manually to the coding rule violation detection circuit 201, the violation of the coding rule is detected at the third and sixth bits of the Oth bit, and a detection signal as shown in FIG. 4 is output.

Here, it is assumed that the input signal (see FIG. 4 (2)) is input in synchronization with the clock signal shown in FIG. 4 (2).

The detection signal and the mask signal input to the mask pulse generation circuit 210 are logically summed by the logical sum gate 211 (see FIG.
It is input to the clock (CK) terminal of.

When the output of the OR gate 211 rises, the output terminal d of the flip-flop 212 becomes "0" (see Figure 4).On the other hand, since the flip-flop 215c is cleared, the Nant gate 244a The input to the launch circuit formed by the NAND gate 214b is "1" on the NAND gate 214a side and '0' on the 214b side.
°, the latch circuit is reset, and the output (i.e. mask pulse) of the Nant gate 214b rises (
(See Figure 4 ■).

Due to the mask pulse, the flip-flops 215a,
Since clearing of the flip-flops 215b and 215c is canceled, the flip-flops 215a and 215b are cleared at the rising edge of the clock signal (see FIG. 4).

“1°° is sent to each output terminal Q in the order of 215c.

At the third rising edge of the clock signal after clearing is released, the output terminal d of the flip-flop 215c becomes "0".
As a result, the output of the Nant gate 214a becomes 1'', and the polarity of this is inverted by the inverter 213 to clear the flip-flop 212, so the output terminal d of the flip-flop 212 becomes 1'' (
(See Figure 4 ■).

The input to the latch circuit is 0'' on the Nant gate 214a side.
, 214b side becomes "1", the latch circuit is set, and the output of the Nant gate 214b becomes 0°', so the mask pulse falls (see Figure 4 ■).Furthermore, the flip-flop 215a, 215b,
215c is cleared again.

In this way, when the mask pulse generation circuit 210 detects the first violation pulse, the mask pulse generation circuit 210
Output one mask pulse for one cycle (see Part 4).

The OR gate 203 takes the logical sum of the violation pulse shown in FIG. 4 (■) and the mask pulse shown in FIG. 4 (■) to generate an error detection signal (■ in FIG. 4).

Therefore, after the first violation pulse, the violation pulse corresponding to the third bit detected by the coding rule violation detection circuit 201 within three clock cycles is deleted. However, since the violation pulse corresponding to the sixth bit is not deleted, the number of code errors is considered to be two, one more than the true code error.

By the way, if the detection signal of the code rule violation detection circuit 201 is deleted by the above-mentioned mask pulse, there is a possibility that the detection signal indicating a real code error will be deleted as well.

For example, when a signal such as ■ in FIG. 5 is input to the code rule violation detection circuit 201, the code violation detection signal is
become that way.

Since the mask pulse generated by the mask pulse generation circuit 210 is as shown in (■) in FIG. 5, the code error detection signal output from the OR gate 203 is as shown in (■) in FIG. Only less than two code errors are detected.

However, as shown in FIG. 5, the probability of receiving a signal in which three consecutive pulses of the same code remain due to a code error is small.

On the other hand, by increasing the length of the mask pulse to, for example, six clock cycles, the violation pulse corresponding to the sixth cycle can also be deleted. However, if the mask pulse is made longer like this I, the probability that a violation pulse corresponding to a real code error will be deleted increases accordingly.

Taking these things into consideration, in the example, the length of the mask pulse was set to three periods of the clock.

The error detection signal obtained as described above is input to the error determination section 240 and accumulated in the timer 242 for a predetermined time T set in the timer 241.

When the number of error detection signals (violation rate) accumulated in the error detection signal 242 exceeds a predetermined value Rv, the determination unit 243 determines that there is a possibility that an abnormality has occurred in the communication line or the terminal equipment. outputs a warning.

After that, the error determination unit 240 further measures the violation rate a predetermined number of times, and if the violation rate is always within the allowable range, it is determined that there is no abnormality in the communication line or the terminal equipment. do.

-J. If the violation rate measurement results always exceed the allowable range, it is determined that an abnormality has indeed occurred in the communication line or terminal equipment.

■Summary of 1 As mentioned above, the violation detection signal detected by the coding rule violation detection circuit 201 is masked with a mask pulse having a length of three clock cycles output by the mask pulse generation circuit 210. do.

Therefore, even if the coding rule violation detection circuit 201 detects a violation intentionally inserted into the code as a code error, the corresponding coding rule violation detection circuit 201
It is possible to delete at least one bit of the violation pulse from the 01 detection signal.

This allows the code error detection circuit to accurately grasp the number of code errors and monitor communication, thereby preventing the terminal device from frequently stopping its operation.

■, O's Yushi.

In the embodiment of the present invention described above, a case has been considered in which the detection signal is deleted by a mask pulse having a length of three clock cycles, but the present invention is not limited to this, and a mask pulse having a predetermined length can be used. This method can be applied as long as the detection signal is deleted by the method.

In addition, in ``correspondence between Examples and Figure 1'',
Although the correspondence between the present invention and the embodiments has been described, those skilled in the art will easily assume that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As described above, according to the present invention, a detection signal corresponding to a code rule violation intentionally included in a code is determined and deleted using a mask pulse of a predetermined length.

This makes it possible to accurately determine the number of code errors and monitor communications, which is extremely useful in practice, as it can prevent terminal equipment from frequently stopping its operation, for example. It is.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of a code error detection circuit according to the present invention, Fig. 2 is a block diagram showing the configuration of a code error detection circuit according to an embodiment of the present invention, and Fig. 3 is a block diagram of the code error detection circuit according to an embodiment of the present invention. A configuration diagram of the mask pulse generation circuit of the code error detection circuit according to the embodiment, FIG. 4 is a timing diagram showing the operation of the code error detection circuit according to the embodiment shown in FIG. 2, and FIG. A timing diagram showing the operation of the code error detection circuit according to the embodiment. FIG. 6 is an explanatory diagram of a bipolar code. 0 is a mask pulse generation means, 3 is an OR gate, 0 is an error judgment unit, 1 is an OR gate, 2215 is a flip-flop, 3 is an in-hake, 4 is a Nant gate, ① is a timer, 2 is a counter, 3 is a judgment Department. In the figure, 101 is a violation detection means, 102 is a mask pulse generation means, 103 is a discrimination means, 201 is a code rule violation detection circuit, and 101 is a violation detection means. Figure ○ ○ ○ / Guigachi Seisaku η theory February map

Claims (1)

[Claims] (1) Violation detection means (101) that detects a violation of the coding rule of a bipolar encoded input signal, and a mask pulse that generates a mask pulse of a predetermined length based on the detection signal of the violation detection means (101). generating means (102); and determining whether or not the coding rule violation detected by the violation detecting means (101) is a signal coding error based on the output state of the mask pulse generating means (102). A code error detection circuit comprising means (103) and configured to detect code errors in a signal.