JPH0244183B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image data processing apparatus, and more particularly to an image data processing apparatus that can obtain image patterns of a plurality of dot sizes by reducing or enlarging the size of an original image pattern.

When reducing an image pattern such as a character pattern, the image pattern is divided into, for example, 3 x 3 blocks, and if the pattern of the blocks is as shown in Figure 1 A, it is converted into a 2 x 2 pattern as shown in B. In this method, the image pattern A, as shown in Fig. 2 A, is reduced to a pattern like A'.
When there are B, C, D... and you want to reduce them to 3x3, for example, a=A, b=B・C, c=D...
As shown in Figure 3, this method uses logic to obtain a reduced pattern.The image pattern is scanned horizontally and vertically, and the image pattern in areas other than the characteristic areas of the image pattern is thinned out line by line. There is a method called.

However, in the above method, there are a large number of patterns to be compared and the processing time is long.In the above method, the reduction processing is performed using a dedicated arithmetic circuit for performing the reduction processing, so the number of circuits increases, and the processing time also takes a long time. Not only this, but also complicated hardware is required. In the above case, when designing a character pattern, the lines and columns to be deleted are determined in advance in areas other than the characteristic parts, and this is added as reduction information.The reduction process is performed based on this reduction information, so the characteristic Not only does the hardware become complicated to detect parts other than the specified areas, but there is also the problem that the degree of freedom during reduction processing is limited.

Therefore, the present invention improves the above problems, and
To provide an image data processing device capable of converting an image pattern into a reduced or enlarged dot pattern with simple hardware and short processing time. For this purpose, the image data processing device of the present invention changes the image size by deleting or inserting part of the image data obtained by reading the image in units of rows or columns. a prediction circuit that reads image data and obtains its prediction data; a prediction error data creation means that creates prediction error data indicating whether or not the prediction data obtained from the prediction circuit matches the image data; A prediction error count comparison means that counts prediction error data in units of rows or columns and compares the magnitude for each row or column of a fixed number of units, and a prediction error count for every fixed number of units based on the output of the prediction error count comparison means. Select the row or column with the least amount of data, and if there are multiple rows or columns with the least amount of data, select one of them according to a predetermined priority order to select the row or column to be reduced or enlarged. The present invention is characterized in that a priority designation means is provided, and the image data is controlled to be reduced or enlarged based on the output of the priority designation means.

By the way, when performing compression processing, including the present application, which is usually performed to transmit image data to another device, a predicted value is calculated from peripheral pixels of the image data, and the calculated predicted value is compared with the actual image data. Comparisons are made to detect errors. This is to set a break between the lengths of compressed data. For example, the continuous position from white to black can be sent as one compressed data, or the position from black to white can be transmitted as one compressed data. It is used for sending data.

The key point of the invention of the present application is that information indicating errors in image data associated with predicted values, which is used when performing this normal compression processing, is used for reduction processing as described below.

Before describing the present invention in detail based on one embodiment, the outline of the present invention will be explained in FIGS. 4 to 6 and 8.
The explanation will be given based on FIG. 9, FIG. 10, etc.

First, as shown in FIG. 5A, reference pixels a, b,
The state of the prediction target pixel x is predicted according to the state of c. The predicted value of the prediction target pixel x is determined by the states of a, b, and c, as shown in FIG. 5(b).

For example, as shown in FIG. 4, for a 30×30 character pattern, a predicted value is determined as shown in FIG. 5, and a match between this predicted value and the actual character pattern is determined. The prediction error shown in FIG. 6 is obtained by setting "0" for "0" and "1" for mismatch. In addition, when calculating the predicted value by scanning horizontally from the top in FIG. 4, the first column,
In the first line, a white pixel "0" outside the character frame is used as a reference pixel. In this way, the prediction error is determined, and the sum of the number of errors "1" is determined for every 5 rows or 5 columns in the horizontal and vertical directions. Then, for each of these units, rows or columns that have a smaller sum of error numbers "1" are selected as deletion candidates when reducing the size. If there are multiple candidates, the one to be deleted is determined according to the ranking numbers shown in FIG. 8C. A small number of errors "1" indicates a portion where the pattern changes little, so it is possible to determine what to delete based on the number of prediction errors. In this way, the rows or columns marked with an x mark outside the frame of FIG. 6 can be determined to be deleted. As a result of deleting the character pattern in the row or column marked with this X, the result is 24 characters as shown in Figure 9.
A reduced character pattern of ×24 bits can be obtained.

Furthermore, when reducing the pattern shown in Figure 10A to 4/5, the prediction error, number of errors, and deleted lines will be as shown in Figure 10B, and the lines marked with an x will be deleted. .

Next, one embodiment of the present invention will be described based on FIGS. 4 to 9.

FIG. 4 shows that characters are read by an optical device, for example,
This is a character pattern obtained by binarizing this.

FIG. 5 is an explanatory diagram for creating a predicted value, in which A shows a prediction reference pixel array and a pixel to be predicted, and B is an explanatory diagram for determining a predicted value of a pixel to be predicted.

FIG. 6 shows the prediction error, the number of errors, and a diagram to be deleted.

FIG. 7 is a prediction error generation circuit diagram and a prediction error transmission restoration diagram used in the present invention. These are known and necessary for character pattern reduction, and are used as preprocessing of the present invention. It is something to be used.

FIG. 8A is a block diagram of an embodiment of the present invention, FIG. 8B is a detailed diagram of the comparison circuit, FIG.

FIG. 9 shows a character pattern obtained by reducing the character pattern shown in FIG. 4 according to the present invention.

In the figure, 1 is character pattern data buffer memory (hereinafter referred to as PDB), 2 is a shift register, and 3
4 is a prediction circuit, 4 is an EOR circuit, 5 is a run-length encoding circuit, 6 is a character pattern compressed data buffer, 7 is a run-length decoding circuit, 8 is a restoration circuit, 9 is a restored character pattern buffer (hereinafter referred to as
RPDB), 10 is a buffer memory, 11 is a memory read control unit, 12 is an error counter, 13
is the row error number register, 14 is the column error number register,
15 is a first switching circuit, 16 is a comparison circuit,
17 is a priority designation circuit, 18 is a second switching circuit, 19 is a deleted row register, 20 is a deleted column register, 21 is a match circuit, 22 is a counter, and 23 is a register.

The PDB 1 is a buffer in which an original pattern as shown in FIG. 4, which is obtained by scanning characters or images with an optical device and converting them into binary data, is set.

The shift register 2 is for simultaneously outputting reference pixels a, b, and c in order to obtain the predicted value of the prediction target pixel x from the reference pixels a, b, and c, as shown in FIG. 5 A and B. be. Here, the first component 2-0 of the shift register 2 outputs the prediction target pixel x shifted by 1 row + 1 bit, and the second component 2-1 outputs the result shifted by 1 row. , the third component 2-2 outputs a signal shifted by one bit.

The prediction circuit 3 is a predicted value generation circuit that calculates the predicted value of the prediction target pixel x from the reference pixels a, b, and c, as shown in FIG. It is configured to output a predicted value. In this case, the values of reference pixels a, b, and c are transmitted from the shift register 2, and for example, when a, b, and c are [1, 1, 1], the values of reference pixels a, b, and c are "1".
It also outputs "0" when it is [1, 1, 0], and can also be configured with a ROM.

The EOR circuit 4 detects whether the predicted value created by the prediction circuit 3 matches the actual original pattern x, and
If they match, "0" is output; if they do not match, "1" is output as an error. Therefore, when processing the character pattern shown in FIG. 4 in the prediction circuit 3,
The EOR circuit 4 outputs "1" and "0" shown in FIG.

The run-length encoding circuit 5 generates a run-length code indicating the number of consecutive bits of "1" or "0", and is used to compress the amount of data transmitted. The prediction error data of "1" and "0" shown in FIG. 6 outputted from the EOR circuit 4 is divided into data with how many consecutive "0" bits and data with how many consecutive "1" bits. It is transmitted as compressed data with a run-length code indicating that.

The character pattern compressed data buffer 6 is a buffer in which compressed data, which is a run-length code outputted from the run-length encoding circuit 5, is held.

The run-length decoding circuit 7 decodes the run-length code transmitted from the character pattern compressed data buffer 6 and outputs "1" as shown in FIG.
This is to decode into prediction error data of "0".

The restoration circuit 8 restores the character pattern shown in FIG. 4 based on the prediction error data transmitted from the run-length decoding circuit 7. The character pattern restored as a result is held in the RPDB9.

The buffer memory 10 is a buffer in which prediction error data of "1" and "0" outputted from the run-length decoding circuit 7 and shown in FIG. 6 is held.

The memory read control unit 11 performs control to read out the prediction error data held in the buffer memory 10 row by row or column by column, and when it is read out row by row, it is fixed by switch _S1 . It is output to the contact S _1-1 , and when it is read out column by column, it is output to the fixed contact S _1-2 .

The error counter 12 is a counter that counts the number of errors "1" included in the prediction error data read from the buffer memory 10 as described above.

The row error number register 13 is a register that holds the count value of error "1" output from the error counter 12 for each row, for example, for each row for five rows.

The column error number register 14 is a register that holds the count value of error "1" outputted from the error counter 12 for each column for each column, for example, for five columns.

The first switching circuit 15 selectively outputs the data transmitted from the row error number register 13 or the column error number register 14.

The comparator circuit 16 detects the smallest value among the number of errors simultaneously output from the first switching circuit 15, and its specific configuration is shown in FIG. 8B. That is, matching circuit 2
1 and a counter 22, and a matching circuit 21
is composed of match detection units 21-0 to 21-4. And the counter 22 is 0, 1, 2...
...30 are output sequentially. Match detection unit 21
Counter 22 with any one of -0 to 21-4
If the matching detection section matches the output numerical value from , the matching detection section that detects the matching outputs "1", and the others output "0" and reset the counter 22. And the match detection unit 21-0
The outputs of the registers 21-4 are transmitted to the register 23 and temporarily held there. For example, as shown in the first five lines on the right side of Figure 6, the number of errors is [0, 4,
8, 4, 0], the first "0" is transmitted to the match detection section 21-0, and the first "4" is transmitted to the match detection section 21-1. Then, the signals are applied to the coincidence detecting sections 21-2 to 21-4 in the order of the number of errors. At this time, since the counter 22 initially outputs the numerical value "0", the coincidence detecting section 21-0 and the coincidence detecting section 2 to which the error number "0" is transmitted.
1-4 outputs a coincidence output "1", and the other coincidence detection sections 21-1 to 21-3 output "0".
Also, as shown in the lower part of FIG. 6, the number of errors [1, 6, 3, 6, 2] in the last five columns is
-0 to 21-4, when the counter 22 outputs "1", the match detection unit 21-
0 outputs a matching output "1", and the others output "0". The counter 22 is then reset to ``0''.
Output.

The priority designation circuit 17 designates a row or column to be deleted, and in the illustrated example, one out of five rows (or five columns) is designated to be deleted. The logic for determining the deletion target is that out of the five rows (or five columns), the row (or column) with the smallest number of errors should be deleted. However, if there are multiple errors with the smallest number of errors, the deletion order is determined based on the order shown in FIG. 8C. This priority designation circuit 17 is a ROM having the logic shown in FIG.
It can be composed of

The second switching circuit 18 is a priority designation circuit 1
7 to be deleted are sequentially transmitted to the deleted row register 19, and columns to be deleted are sequentially transmitted to the deleted column register 20.

The deleted row register 19 is connected to the second switching circuit 1.
For example, if the line to be deleted transmitted from 8 is a register set for one image and the prediction error data shown in FIG. The rows marked with an x mark) are filled in sequentially.

The deletion column register 20 is a register in which the row to be deleted transmitted from the second switching circuit 18 is set for one image, for example, and in the case of prediction error data shown in FIG. The selected deletion columns (the columns marked with an x in the lower part of FIG. 6) are filled in in sequence.

Next, the operations shown in FIGS. 7 and 8 will be explained with reference to other figures.

(1) In FIG. 7, when the original pattern shown in FIG. 4 is set in PDB 1, shift register 2 and prediction circuit 3
A predicted value as described above is output for the pattern 1, and this predicted value is compared with the data set in PDB1 in the EOR circuit 4. Based on the match/mismatch, the EOR circuit 4 outputs prediction error data as shown in FIG.
This prediction error data is compressed into a run-length code by a run-length encoding circuit 5, sent out, and held in a character pattern compressed data buffer 6. The run-length code held in this manner is transmitted to the run-length decoding circuit 7, where it is restored to the prediction error data shown in FIG. The restored prediction error data is then transmitted to the restoration circuit 8, whereby the original pattern shown in FIG. 4 is reproduced. In this way, the original pattern obtained by the known compression and decompression process is held in the RPDB9.

(2) On the other hand, the prediction error data restored by the run-length decoding circuit 7 is held in the buffer memory 10, as shown in FIG. 8A. Then, the memory read control unit 11 first reads the prediction error data held in the buffer memory 10 into the sixth buffer memory 10.
Read out one line at a time in the horizontal direction starting from the upper left of the figure. At this time, the movable contacts S _1-0 of switches S ₁ and S ₂ and
S _2-0 is connected to fixed contacts S _1-1 and S _2-1 , respectively. Therefore, when the first row of prediction error data is read by the memory read control unit 11, the error counter 12 counts "1" that exists in the prediction error data, but "1" is 0, so error counter 1
2 outputs "0", which is set in the row error number register 13. In this way, the memory read control unit 11 sequentially reads the second row, the third row, and so on.
and outputs the prediction error data for each row. In response to this, the error counter 12 is set to "1" for each line.
The number of row errors is counted sequentially, and this is stored in the row error number register 1.
Set to 3.

(3) When the count values [0, 4, 8, 4, 0] for each row from the 1st row to the 5th row are set in the row error number register 13, the first switching circuit 15 The numerical value is transmitted to the comparison circuit 16. The comparator circuit 16 selects among these numerical values,
Since "1" is output in the first and fifth rows, which naturally indicate the smaller value "0", and "0" is output in the other rows, "10001" is output in this case.
This is then transmitted to the priority designation circuit 17, and the priority designation circuit 17 outputs "1" on the fifth line based on the order shown in FIG. The signal is transmitted to the second switching circuit 18.The second switching circuit 18 sets the signal indicating this fifth row in the deleted row register 19.In this way, the deleted row register 19 contains the signals indicating the fifth row. It is set that the fifth row should be deleted from the unit group of five rows.

(4) After the lines to be deleted are determined for the 1st to 5th lines in this way, the line error number register 1
3 is set to the number of "1"s [4, 3, 5, 3, 0] in the 6th to 10th lines. This is then similarly transmitted to the comparator circuit 16,
The 10th row with the smallest value “0” is “1”,
The other rows become "0" and are output to the priority designation circuit 17. Thus, the priority designation circuit 17 outputs a signal indicating the 10th row of this "1"("1" to the fifth output line), and this is transmitted to the deletion row register 19 via the second switching circuit 18. . Thus, the deleted line register 19 contains
10th unit group from rows 6 to 10
It is set that the row should be deleted. This is what happens in lines 11 to 15, lines 16 to 20...
As a result, the deletion row register 19 contains the 12th row as the row to be deleted.
Rows 17, 23, and 29 will be set.

(5) After the lines to be deleted are selected for each horizontal line in FIG.
1 reads out prediction error data from the buffer memory 10 one by one in the vertical direction from the upper left of FIG. At this time, the movable contacts S _1-0 of switches S ₁ and S ₂
and S _2-0 are now fixed contacts S _1-2 and S _2-2
Connect with. Then, in the same manner as described above, columns to be deleted are selected for each of the first to fifth columns and the sixth to tenth columns, and set in the column error number register 14. As a result, the column error number register 14 contains the first
row, row 8, row 13, row 17, row 23 and row
26 columns are set as columns to be deleted.

(6) Based on the rows and columns set in the deletion row register 19 and deletion column register 20 in this way, by deleting the original pattern of rows and columns set in the RPDB 9 of FIG. The original pattern of x30 bits can be reduced to a pattern of 24 x 24 bits as shown in FIG.

In addition, in the above explanation, the pattern is 30×30 to 24×
Although an example in which the size is reduced to 24 has been described, it is possible to reduce the size to an appropriate size by changing the unit to be deleted from 5 to 4, 3, 6, etc.

Then, the size of the pattern can be expanded by inserting the row or column with the smallest number of errors found as described above into the next row or column. If there are multiple rows or columns with a small number of errors, the rows or columns to be inserted can be selected using the same priority order as described above.

Although character patterns have been described in the above embodiments, the present invention is of course not limited to this.

As explained above, according to the present invention, a prediction error can be obtained by scanning a character pattern once with a very simple configuration, and this prediction error can be calculated by
By counting in the column direction, it is possible to detect rows and columns to be deleted or inserted very easily, making it possible to reduce or enlarge the image very quickly and economically, and also to perform a fixed number of units. Since the row or column to be reduced or enlarged is selected for each row or column, the transformation can be performed in a very natural manner.

[Brief explanation of the drawing]

Figures 1 to 3 are illustrations of conventional image pattern reduction methods, Figure 4 is an example of a character pattern, Figure 5 is an illustration of creation of predicted values, and Figure 6 is prediction error, number of errors, and deletion. Target diagram, Figure 7 is a prediction error generation circuit and prediction error transmission restoration diagram, Figure 8A is a configuration diagram of an embodiment of the present invention, Figure 8B is a detailed diagram of a comparison circuit, Figure 8C is a deletion priority FIG. 8D is an explanatory diagram of the priority designation circuit operation, FIG. 9 is a character pattern obtained by the present invention, and FIG. 10 is an explanatory diagram of another operation of the present invention. In the figure, 1 is a character pattern data buffer memory, 2 is a shift register, 3 is a prediction circuit, and 4 is a
EOR circuit, 5 is a run-length encoding circuit, 6 is a character pattern compressed data buffer, 7 is a run-length decoding circuit, 8 is a restoration circuit, 9 is a restored character pattern buffer, 10 is a buffer memory, 1
1 is a memory read control unit, 12 is an error counter,
13 is a row error number register, 14 is a column error number register, 15 is a first switching circuit, 16 is a comparison circuit, 17 is a priority designation circuit, 18 is a second switching circuit, 19 is a deletion row register, and 20 is a deletion column register. , 21 is a matching circuit, 22 is a counter, 23
indicate registers, respectively.

Claims (1)

[Scope of Claims] 1. An image data processing device that changes the image size by deleting or inserting part of the image data obtained by reading the image in units of rows or columns, comprising: reading the image data; a prediction circuit that obtains the prediction data; a prediction error data creation unit that creates prediction error data indicating whether or not the prediction data obtained from the prediction circuit matches the image data; a prediction error count comparison means that counts in units of columns and compares the magnitude for each row or column of a fixed number of units; A priority designation means is provided for selecting a row or column to be reduced or enlarged by selecting an example, and selecting one of them according to a predetermined priority when there are a plurality of rows or columns that are at least small; An image data processing apparatus characterized in that the image data is controlled to be reduced or enlarged based on the output of the priority designation means. 2. Image size is increased by enlarging the image data by inserting the same data as the selected row or column into the row or column next to the row or column selected by the priority designation means. An image data processing apparatus according to claim 1.