JPH0244514Y2 - - Google Patents

Description

[Detailed description of the invention] [Technical field of the invention] The present invention relates to a power combiner using field effect transistors (hereinafter referred to as FETs), and in particular, relates to a power combiner using field effect transistors (hereinafter referred to as FETs).
This invention relates to a power combiner that combines power using FET chips.

[Technical background of the invention]

A conventional power combiner of this type is constructed as shown in FIG. 1, and input terminals 1 and 2 are supplied with signals to be combined, and these signals are amplified by amplifiers 3 and 4, respectively, to generate the amplified signal. is led to a power combining section 5 for combining, and then taken out from an output terminal 6.

[Problems with background technology]

Such conventional power combiners require an amplifier for each signal to be combined. It is desirable that the signals to be combined be in phase. Although it is generally not easy to adjust other characteristics such as gain of an amplifier and phase characteristics to desired ones, such adjustment must be performed if there are a plurality of amplifiers.

Since the power combiner requires multiple 1/4 wavelength lines and resistors, and multiple amplifiers, it is difficult to downsize the power combiner, and there are problems in that it is expensive due to the large number of components. .

[Purpose of invention]

The present invention was devised in view of the above points, and an object of the present invention is to provide a small and inexpensive power combiner that requires almost no adjustment.

[Summary of the idea]

In this invention, each cell of a semiconductor chip in which a plurality of FET cells each formed by a drain, gate, and source are arranged is divided into groups, and a gate electrode is provided for each group to serve as an input terminal for signals to be synthesized. The above object is achieved by making the drain electrode common to all cells and using this drain electrode as an output terminal for the combined signal.

[Example of idea]

Here, before explaining embodiments of the present invention, the structure of a general FET will be explained.

FIG. 2 is a diagram showing a typical FET chip. An FET chip has an epitaxial layer grown on a semi-insulating substrate, on which ohmic electrodes for source S and drain D and a gate shot key barrier are formed. This chip can be said to have a large number of cells arranged in the A section, each including a drain, source, and gate as one unit (referred to as a cell). The portion where the gate and source intersect, such as portion B, has an overlay structure. A common drain electrode D and gate electrode G are provided for a plurality of such cells, and the chip is mounted on a package made of ceramic and a heat sink conductor, and the drain electrode, gate electrode, and source electrode are mounted on a package made of ceramic and a heat sink conductor. is connected to the electrode conductor by a bonding wire. Because of this structure, each cell is connected in parallel and functions as a single FET.

Now, in the present invention, as in the embodiment shown in FIG.
gate electrodes G ₁ and G ₂ are provided for each group, and one common electrode D is provided for the drain. Although the FET thus obtained is a single chip, it functions as if it were two FETs. FIG. 4 shows its equivalent circuit. Therefore, when signals to be combined are applied to the gate electrodes G ₁ and G ₂ , they are amplified, and the combined signals appear at the drain electrode D.

In this way, power can be combined in a device using one FET chip. Since the two FETs are formed on the same chip, there is almost no variation in characteristics between them, and therefore there is almost no need for adjustment. In addition, this FET chip
As shown in the figure, the main components of amplifiers 3 and 4 were each housed in one package in the conventional example (Figure 1).
As can be seen from the comparison with the conventional example, which requires FETs, that is, at least two packages of FETs, the power combiner of this embodiment is significantly miniaturized. In FIG. 5, 11 and 12 are gate electrode conductors, 13 is a drain electrode conductor, 14 is a heat sink that also serves as a source electrode conductor, and 15 is a mounting screw hole.

FIG. 6 is a configuration diagram showing an example in which such a power combiner is used in a power combination stage of a four-phase phase modulator.
21 is an input terminal, 22 is a distributor, 23 and 24 are 0-π modulators that individually modulate the distributed signals, and 2
5 is a power combiner of the present invention, 26 is an output terminal, 27
is a terminator of the distributor 22.

In the above embodiment, two signals are to be synthesized, but three or more signals may be synthesized by dividing the gate of the FET into three or more. Also, when combining two or more signals,
The number of cells divided within the FET does not need to be the same, and can be arbitrarily determined depending on the level of the signals to be combined.

[Effect of idea]

As explained above, according to the present invention, since signals are combined using one-chip FET, there is almost no need for adjustment, and a small and inexpensive power combiner can be provided.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of a conventional power combiner, Fig. 2 is a structural diagram of a general FET, Fig. 3 is a structural diagram of an FET according to an embodiment of the present invention, and Fig. 4 is its equivalent circuit diagram.
FIG. 5 is an external view of the FET shown in FIG. 3, and FIG. 6 is a configuration diagram of a four-phase phase modulator to which the present invention is applied. _G1 , _G2 ...Gate electrode, D...Drain electrode,
S... Source electrode, 1, 2... Input terminal, 6...
Output terminal.

Claims (1)

[Scope of utility model registration request] A semiconductor chip in which a plurality of field effect transistor cells each formed by a drain, a gate, and a source are arranged, has a drain electrode and a source electrode to which the drain and source of each cell are connected in common, and one or more cells. A power source characterized in that a plurality of gate electrodes each having a gate connected to each other are provided, each of the plurality of gate electrodes is used as an input terminal for a signal to be synthesized, and a drain electrode is used as an output terminal for the synthesized signal. Synthesizer.