JPH0244926A - Power line carrier receiver - Google Patents

Abstract

PURPOSE:To improve the transmission efficiency by varying a reception level of a carrier signal received in response to noise condition of a power line and a reception discrimination rate of the carrier signal. CONSTITUTION:A binarizing circuit 8 binarizes a carrier signal with respect to a reference voltage, a counter circuit 9 frequency-divides the binarized carrier signal with a frequency division ratio set by a frequency division ratio setting means (switch) 9b and counts the result. A sub bit discrimination function 11c applies sub bit discrimination based on the result of comparison between the basic count and the count and a reference level control function 11e revises the level of the reference voltage. Thus, the transmission distance is adjusted in response to a noise voltage on an indoor distribution line 2. Thus, the transmission efficiency is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power line carrier/receiver that transmits data via a power line.

[Prior Art] FIG. 8 is a block diagram of a receiving section of a conventional power line transport device disclosed in, for example, Japanese Patent Application Laid-Open No. 81-280723. In FIG. 8, (1) is a commercial power supply, (2) is a power line, (5) is a receiving circuit consisting of a coupling circuit (3) and an amplifier circuit (32), (6) is a power synchronization detection circuit, (31) is a control circuit, and (33) is a counter.

The receiving circuit (5) is coupled to the power line (2) and receives the signal a from the power line (2). Signal a is shown in Figure 9 (a
), a rectangular waveform carrier signal is modulated by logical data, and this modulated signal is further superimposed on a sinusoidal waveform commercial power supply (1).

The coupling circuit (3) removes the frequency component of the commercial power supply (1) from the signal a and outputs a modulated signal C, as shown in FIG. 9(C).

The power supply synchronization detection circuit (6) detects the zero-crossing point of the commercial power supply (1) and outputs the zero-crossing signal shown in FIG. 9(b). This zero-crossing signal is used to determine the timing for decoding logical data.

The amplifier circuit (32) amplifies the modulation signal C output by the coupling circuit (3) and outputs it to the counter (33).

A counter (33) counts the number of pulses of the carrier signal obtained by demodulating the modulated signal a. Note that the counter (33) is reset by the reset input of the control circuit (31).

The control circuit (31) decodes the logical data and performs processes such as controlling a load (not shown) and changing the display according to the contents.

The receiving section of the conventional power line carrier shown in FIG.
As shown in the figure, one bit of logical data is transmitted per half cycle of the frequency of the commercial power supply (1). This logic data corresponds to logic "1" when there is a carrier signal, and corresponds to logic "0" when there is no carrier signal. Therefore, the logical data in FIG. 8 is transmitting information of "10110".

Next, the operation of the receiving section of the conventional power line carrier device will be explained.

When the signal a shown in FIG. 9(a) is input to the receiving circuit (5), the coupling circuit (3) takes out the carrier signal, the amplifier circuit 32) amplifies the carrier signal, and the counter (33) Output to. The counter (33) counts the number of rising edges or falling edges of the carrier signal output by the amplifier circuit (32), and outputs the count value to the control circuit (3).

On the other hand, the power synchronization detection circuit (6) detects the zero cross point of the commercial power supply (1) and transmits the zero cross signal to the control circuit (3).
1) Output. The control circuit (31) outputs a reset signal to clear the counter (33) to zero every time the power supply synchronization detection circuit (6) outputs the zero-cross signal b (synchronization pulse), and after a certain period of time has passed since the zero-clear. The count value of the counter (33) is read out, and the presence or absence of the carrier signal is determined based on that value.

For example, if the frequency of the commercial power supply (1) is 50 Hz and the frequency of the carrier signal is 100 KHz, the power synchronization detection circuit (
6) outputs a zero-crossing signal and the control circuit (31) reads the count value after SMS, the count value read by the control circuit (31) when there is a carrier signal is 500. Therefore, if the control circuit (31) determines that there is a carrier signal when the count value is 500±25, it will obtain a frequency selectivity of 100±5 KHz.

[Problems to be Solved by the Invention] By the way, in the receiving section of the conventional power line carrier device having the above configuration, since the noise state of the power line (2) which is the transmission path is unstable depending on the location and time, If carrier signals are discriminated by fixing the carrier signal, there are problems in that the transmission distance decreases and the transmission efficiency decreases due to transmission errors.

The present invention has been made to solve the above problems,
It is an object of the present invention to provide a power line carrier receiving device that can vary the reception level of a received carrier signal depending on the noise state of a power line (2) and easily vary the reception determination rate of the carrier signal.

[Means for Solving the Problems] A power line carrier/receiver according to the present invention includes a binarization unit that binarizes the carrier signal by comparing the carrier signal with a predetermined reference voltage, and a binarization unit that binarizes the carrier signal by comparing the carrier signal with a predetermined reference voltage. a counting means for dividing the frequency by a predetermined frequency division ratio and counting the number of pulses of the frequency-divided carrier signal for a predetermined time; a frequency division ratio setting means for setting the frequency division ratio; and a preset basic count. a comparison means for comparing the value with the count value of the counting means; a sub-bit determination means for making a sub-bit determination based on the comparison result of the comparison means; and a change in the magnitude of the reference voltage based on the comparison result of the comparison means. and reference voltage control means.

[Function] In the power line carrier/receiver having the above configuration, when the binarization means compares the carrier signal with a predetermined reference voltage and binarizes it, the counting means converts the binarized carrier signal into a frequency division ratio setting means. The frequency is divided by the frequency division ratio set by , and the number of pulses of the frequency-divided carrier signal is counted for a predetermined period of time, and the comparing means compares a preset basic count value with the count value of the counting means.

At this time, the sub-bit determination means makes a sub-bit determination based on the comparison result, and the reference voltage control means changes the magnitude of the reference voltage based on the comparison result.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block circuit diagram of a power line carrier/receiver device according to an embodiment of the present invention. In Figure 1, (1) is the commercial power supply, (2) is the indoor power line, and (3) is the indoor power line (2).
(4) is a transmitting circuit, (5) is a receiving circuit, (6) detects the zero cross point of the commercial power supply (1),
This is a power supply synchronization detection circuit that outputs a zero-crossing signal synchronized with the zero-crossing point.

The receiving circuit (5) includes a resonant amplifier circuit (7) and a binarization circuit (
8), counter circuit (9), reference voltage generation circuit (10)
and a microcomputer (11).

The resonant amplifier circuit (7) removes the frequency component of the commercial power source (1) from the signal a, extracts a (modulated) carrier signal, and amplifies it. Signal a is logical data (4a
) is used to modulate the carrier signal (4b), and this modulated signal is further superimposed on the commercial type i (L).

The binarization circuit (8) is composed of a comparator (8a) whose reference voltage is set by the reference voltage generation circuit (10), and converts the carrier signal output from the resonant amplifier circuit (7) into two.
Value.

The counter circuit (9) includes a first counter (9a) that counts the number of rising edges or falling edges of the carrier signal output by the binarization circuit (8), a switch (9b) forming a frequency dividing circuit, and a NAND It consists of a circuit (9C) and a second counter (9d).

The reference voltage generation circuit (10) is set at a level at which the binarization circuit (8) binarizes the carrier signal by the microcomputer (11).
Set by.

The microcomputer (11) has a second counter (9d
) count value storage function (lla
), a reference count value storage function (llb) that stores a reference count value, a count value storage function (1, 1a)
Count value and reference count value storage function (]1.b
) sub-bit judgment function (
1-1c), a reference level value storage function (li
d) and a reference level value control function (lie) that controls the reference level value storage function (lid).

Note that these functions can be easily realized by a program.

The power line carrier receiving device shown in FIG. 1 is used in an indoor power line carrier control system as shown in FIG. In FIG. 2, (21) is a block filter that prevents the carrier signal from leaking indoors, (22) is a power line carrier/receiver device connected to an appropriate position of the indoor power line (2), and serves as a controller for remote control; (23a) and (23b) are power line carrier/receiver devices as remotely controlled adapters;
24a) and (24b) are adapters (23a) and (2
3b) is the load connected to.

Next, the operation of the power line carrier/receiver shown in FIG. 1 will be explained with reference to FIGS. 3, 4, 5, 6, and 7.

Note that FIG. 3 is a diagram showing a communication procedure by the power line carrier/receiver device shown in FIG. 1. FIG. 4 is a diagram showing the structure of a packet P transmitted to the power line (1). FIG. 5 is an explanatory diagram of the frequency division ratio. FIG. 6 is a timing chart of sub-bit reception processing. FIG. 7 is a flowchart of sub-bit reception processing by the power line carrier receiving device shown in FIG.

First, a transmission request 1? is sent from the master controller (22) to the slave adapter (23a)? When EQ occurs, the microcomputer (11) of the controller (22)
) is based on the logic data (4a) according to the transmission content and the zero-cross signal detected by the power synchronization detection circuit (6).
The logic data (4a) is outputted to the transmission circuit (4) together with the carrier signal (41).

The transmitting circuit (4) modulates the carrier signal (4b) with the logical data (4a) and outputs the modulated carrier signal to the indoor power line (2) via the coupling circuit (3). The carrier signal (4b) is superimposed on the commercial power supply (1) and connected to the indoor power line (
2) to the adapter (23a).

The carrier signal (4b) is transmitted as a packet P consisting of a priority code PC, self address SA, destination address DA, control command CW, data length BC, data DATA, and frame check code FCC, as shown in Fig. 4. be done.

The adapter (23a), which is a slave device, is the controller (22)
The carrier signal outputted by the receiver is inputted to the receiving circuit (5) via the coupling circuit (3).

When the resonant amplifier circuit (7) demodulates the signal on which the commercial power supply (1) is superimposed according to the zero-crossing signal detected by the power supply synchronization detection circuit (6), and extracts and amplifies the modulated signal, the binarization circuit ( 8) Binarize the amplified modulation signal at a level set by the reference voltage generation circuit (10).

The first counter (9a) counts the number of rising edges or falling edges of the binarized carrier signal. The count value of the first counter (9a) is divided by a frequency division ratio according to the on/off state of the switch (9b), and is input to the second counter (9d) via the NAND circuit (9C). . The frequency division ratio is determined by setting the switch (9b) in Fig. 5(a) and Fig. 5(
b) and as shown in Figure 5(c), 1
1.2:1 and 3.1.

The second counter (9d), like the first counter (9a), counts the number of rising edges or falling edges of the frequency-divided carrier signal.

On the other hand, the power synchronization detection circuit (6) detects the zero-crossing point of the commercial power source (1) and outputs a zero-crossing signal to the microcomputer (11).

As shown in Figure 6, the microcomputer (11)
After time t2 has elapsed from the time when the zero-cross signal was output, the first counter (9a) and the second counter (9d
) to reset. This reset causes the counter (9
aL (gd) starts counting the “○” sub-pits I-Co.

The microcomputer (11) stores the count value of the second counter (9d) in the count value storage function (l
la).

Furthermore, when the microcomputer (11) resets the counter (9a) and the counter (9C) after time t4 has elapsed after storing the count value of the second counter (9d), the counters (9a) and (9d) 1” Start counting sub-bit C1.

The microcomputer (11) stores the count value of the second counter (9d) by the count value storage function (lla) after time t5 has elapsed since the start of counting of the "1" sub-bit C.

The microcomputer (11) has a count value storage function (
1, 1a), when the count value of the second counter (9d) is stored, the operation shown in the flowchart of FIG. 7 is performed.

(1) Steps 81 to S4 The microcomputer (11) has a count value storage function (
When the count value of the second counter (9d) is stored (step S1), it is determined whether it is the pause time WT (step S2).

When the microcomputer (11) does not have a pause time WT, the count value of the second counter (9d) is "0" and the reference count value of sub-bit co (t3x f 1lz)
(Step 33)
. For example, when the frequency f of the carrier signal (4b) is 125 old, the standard count value is 2.8 m5X125 KH
Since z-150, 10% of the reference count value is 35
0 XO,l =35.

The microcomputer (11) has a second counter (9d
) is 10% or more of the reference count value, the reception flag is set (step S4), the sub-bits are determined, and the packet P sent by the controller (22) is demodulated.

The reception judgment rate can be changed by changing the first counter (9) as described above.
This is done by frequency-dividing the output of step a) by switching a switch (9b) and counting it with a second counter (9d). Therefore, the reception determination rate can be changed without changing the reception determination rate by the microcomputer (11).
(see step S3).

For example, set the reception judgment rate to 10%, 20%, 30%, or 40%.
%, set the division ratio to 1: ], 2, 1.31 or 4
・Set it to 1.

(2) Steps 85 to S8 After the adapter (23a) completes receiving the packet, it immediately returns an ACK to the controller (22) and ends the communication. After returning the ACK, during the pause time WT (step S2), the microcomputer (11) calculates the count value of the second counter (9d) stored by the sub-bit determination function (11, c) or the count value storage function (lla). is larger than the reference count value stored by the reference count value storage function (11, b) (step S5).
Note that this pause time WT corresponds to the time for sending 3 bits (3/2 period of the power supply frequency). Further, the pause time WT is detected by monitoring the packet hp and ACK.

The microcomputer (11) has a second counter (9d
) is larger than the reference count value, the reference level value control function (llb) performs "r level INc processing" (step S6), and when it is smaller, the reference level value control function (llb) performs "level DEC processing". '' (step 37) Note that the ``level INC processing'' increases the level stored by the reference level value storage function (lid) by one. Also, “Level D
"EC processing" is to decrease the level stored by the reference level value storage function (1], d) by one.

Furthermore, the reference level value storage function (1, 1, d) stores the reference level value changed by the "level INC processing" or the "r level DEC processing" (step 38).

The reference voltage generation circuit (10) converts the changed reference level value from digital to analog, and outputs it as a reference voltage to the comparator (8a) of the binarization circuit (8). This operation makes it possible to control the magnitude of the received voltage according to the noise condition of the indoor power line (2). That is, when the counter value of the second counter (9d) is larger than the reference count value, the reference level value is increased, and when the counter value of the second counter (9d) is smaller than the reference count value, the reference level value is decreased. It turns out.

Note that when a transmission request REQ is generated from the adapter (23b) to the controller (22), the adapter (23a)
) or ACK, and after the pause time WT has elapsed, the adapter (23b) transmits data using the same transmission procedure as that performed by the controller (22).

Furthermore, in this embodiment, a binarization circuit (8) and a counter circuit (9) are used.
), or install an integrating circuit instead of the counter circuit (9) and convert the detection voltage of the integrating circuit to the comparator (9).
8a) may be used as the reference voltage.

[Effects of the Invention] As explained above, according to the present invention, the binarization means binarizes the carrier signal using the reference voltage, and the counter means binarizes the binarized carrier signal by the frequency division ratio setting means. The frequency is divided by the set frequency division ratio and counted. Based on the comparison result between the basic count value and the count value by the comparison means, the sub-bit judgment means makes a sub-bit judgment, and the reference voltage control means or the reference voltage control means Since the magnitude of the voltage is changed, it is possible to obtain a power line carrier/receiver device that can adjust the transmission distance according to the noise voltage of the indoor power line and improve the transmission efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of a power line carrier/receiver according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of an indoor power line carrier control system that utilizes the power line carrier/receiver shown in FIG. 1, and FIG. The figure is an explanatory diagram of the communication procedure by the power line carrier/receiver shown in Fig. 1, Fig. 4 is an explanatory diagram of the packet P transmitted on the indoor power line (2), Fig. 5 is an explanatory diagram of the frequency division ratio, 6 is a timing chart of sub-bit reception processing, FIG. 7 is a flowchart 1 of sub-bit reception processing by the power line carrier receiving device shown in FIG. 1, and FIG. 8 is a block diagram of the receiving section of the conventional power line carrier device. FIG. 9 is a signal waveform diagram of each part of the receiving section of the conventional power line carrier device shown in FIG. 8. In each figure, 1 is a commercial power supply, 2 is an indoor power line, 3 is a coupling circuit, 4 is a transmitting circuit, 5 is a receiving circuit, 6 is a power synchronization detection circuit, 7 is a resonance amplifier circuit, 8 is a binarization circuit, 8a is a comparator, 9 is a counter circuit, 9a19d is a counter, 9b
9c is a switch, 9c is a NAND circuit, 10 is a reference voltage generation circuit, 11 is a microcomputer, Lla is a count value storage function, 11. b is a reference count value storage function, li
e is a sub-bit determination function, lid is a reference level value storage function, and lie is a reference level value control function. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] In a power line carrier/receiver device having a coupling means for extracting a carrier signal modulated by logical data superimposed on a commercial power source from a power line of the commercial power source, binarization converts the carrier signal into a binary value using a predetermined reference voltage. means for frequency-dividing the carrier signal binarized by the binarizing means at a predetermined frequency division ratio, and counting means for counting the number of pulses of the frequency-divided carrier signal for a predetermined time; A dividing ratio setting means to set, a comparison means for comparing a preset basic count value and a count value of the counting means, and a sub-bit determination means for making a sub-bit determination based on the comparison result of the comparison means. , and reference voltage control means for changing the magnitude of the reference voltage based on the comparison result of the comparison means.