JPH0244967A - Large scale integrated circuit for coding and decoding picture signal - Google Patents

Abstract

PURPOSE:To prevent generation of mistake on the circuit design and on manufacture at the start of manufacturing by not only discriminating defective chips at chip test but also confirming the operation as to a prescribed block of an internal circuit. CONSTITUTION:The circuit consists of a system path interface circuit 1, an image path interface circuit 5, a table retrieval circuit 2, a mode discrimination picture circuit 4a, a picture decoding circuit 4b, a change point detection circuit 4c, and a sequencer circuit 3. Not only the test of the entire chip but also the single of composite function test of the mode discrimination picture circuit 4a, a picture decoding circuit 4b, the change point detection circuit 4c is conducted. Thus, the discrimination of the propriety of the single function and also the composite function are facilitated to strengthen the chip test.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a large-scale integrated circuit for encoding and decoding image signals used in facsimile machines, etc., and particularly for encoding and decoding using MH, MR, and MMR encoding systems. This invention relates to large-scale integrated circuits for image signal encoding and decoding.

Conventional technology Currently, the encoding method for facsimile is CC.
According to Recommendations T and 4 of the International Telegraph and Telephone Advisory Committee (ITT), the MH encoding method for one-dimensional encoding and the MR encoding method for two-dimensional encoding have been internationally standardized.

Here, the MH encoding method is a method that detects changing points of the encoded line image signal and uses Mu codes corresponding to the run length and whether the run is black or white. Terminating codes corresponding to run lengths from 0 to 63 as shown in FIG. 7(a), and FIG. 7(b)
As shown in , there is a meter knob code for each run length of 64 runs from 64 to 2560. That is,
Runs of 64 or more are encoded by a combination of a make-up code followed by a terminating code. Also, Ml'? , the encoding method detects the change point of the encoded line image signal and the change point of the reference line (line immediately before the encoded line) image signal, and sequentially encodes the encoded line from the relative position. It is a method. In this MR encoding method, the changing points of the encoded line and the reference line are defined as follows.

ao, the change point that is the starting point of the encoded line At the beginning of the encoded line, ao is placed on the virtual white change point immediately before the first pixel of the line. a,) during encoding of the code line.
The position of is defined by the previous code mode.

al a on the encoding line. First change point to the right C2: First change point to the right of al on the encoding line b+' A of the change pixels on the reference line. To the right is a. First change point b2 having the opposite color: First change point to the right of bl on the reference line FIG. 8 shows an example of the positional relationship of the above-mentioned change points.

Still, FIG. 9 shows the classification of modes according to the relative positions of the change points and the corresponding codes.

The procedure for determining the mode will be explained using FIG. 9.

Step 1 (7) When b2 exists on the left side of al, it is detected as a bus mode and encoded using this mode code word '0001'. After this, the pixel directly below b2 becomes the new starting pixel a. becomes.

(b) If the pass mode is not detected, proceed to step 2.

Step 2 b) Determine the absolute values of the relative distances a, b,.

(b) If +l≦3, it is detected as a vertical mode and the distances of a and b are encoded as shown in FIG. After that, pixel a becomes the new starting pixel a. Totoru.

al b, >o indicates that al is on the right side of bl and is expressed as VR; a, b, <O indicates that a is on the left side of bl and is expressed as vL.

('7) lal b2 If 1>3, it is detected as a horizontal mode, and as shown in FIG. 9, the code '001' is followed by a. A, and a, C2 are each subjected to one-dimensional encoding M (ao a, ), M (a, C2). After this, pixel a2 becomes the new starting pixel a. Totoru.

Further, regarding the MMR encoding method, the encoding algorithm is the same as the MR encoding method.

A large-scale integrated dedicated hardware circuit (hereinafter referred to as CODEC-LSI) is usually used in the MH-MR/MMR encoding/decoding circuit in a conventional facsimile machine.

Problems to be Solved by the Invention However, when starting up production of such a CODEC-LSI, there is a possibility that errors in circuit design or manufacturing errors may occur, and it is necessary to carry out a thorough inspection.

For this reason, there is a method of actually inputting a constant image signal to the CODEC-LSI, extracting the code of each Mu, MR, and MMR encoding system and comparing it with a predetermined code, or conversely, a method of inputting a constant image signal to the CODEC-LSI.

A possible method is to input a predetermined code for each of the MR and MMR encoding systems and compare the restored image signal with the predetermined image signal, but in this case, the C0DEC-LSI
There was a problem in that it was only possible to distinguish between good and bad chips as a whole.

The present invention has been made in view of the above-mentioned problems, and is an image signal code that can not only distinguish between good and bad chips as a whole during chip testing, but also check the operation of predetermined blocks of internal circuitry. The purpose is to provide large-scale integrated circuits for encoding and decoding.

Means to Solve the Problem The above problem involves a system bus interface circuit that inputs and outputs encoded data, an image that inputs and outputs encoded line image signals, reference line image signals during two-dimensional encoding, and restored image signals. A bus interface circuit inputs the change point address of the encoded line and the change point address of the reference line during two-dimensional encoding, determines and outputs the encoding mode, and determines and outputs the encoding mode during two-dimensional decoding. a mode determination circuit that inputs length address information, inputs a change point address of a reference line, inputs color information and decoded run length address information during one-dimensional decoding, and outputs image restoration data; An image restoration circuit inputs restoration data to restore an image, and inputs an encoded line image signal and a reference line image signal during two-dimensional encoding, and calculates a change point address of the encoded line and a change point address of the reference line. In addition to outputting it to the mode determination circuit, it also outputs the changing point address of the encoded line, and when performing one-dimensional encoding, inputs the encoded line image signal and outputs color information and changing point address, and when performing two-dimensional decoding, it outputs the color information and changing point address. a change point detection circuit that inputs a reference line image signal and outputs a change point address of the reference line to the mode determination circuit; and a change point detection circuit that inputs the encoding mode and code run length of the encoded line during two-dimensional encoding. During dimensional encoding, the color information and the code run length of the encoded line are input, and the code data is output to the system bus interface circuit, and the code data is input from the system bus interface circuit, and during two-dimensional decoding, the code data is output to the system bus interface circuit. A table search circuit that outputs the decoding mode and a decoded run length to the mode determination circuit, and outputs color information and the decoded run length during one-dimensional decoding, a data memory, and an arithmetic unit. During two-dimensional encoding, the change point address of the encoded line signal is input, the code run length of the encoded line is calculated and output to the table search circuit, and the decoding thanks is input during one-dimensional and two-dimensional decoding. and a sequencer circuit that calculates the address information of the decoded run length and outputs it to the mode determination circuit and controls each of the circuits. Under the control of the sequencer circuit, the rehearsal data is transferred from the system bus interface circuit to the data. The change point address data is input to the change point detection circuit via a memory and output to the mode determination circuit, and the mode determination circuit outputs encoded mode data to the system bus interface circuit via the data memory. Image signal encoding/decoding is achieved by large-scale integrated circuits. Further, a first-in, first-out memory is provided for inputting data from the system bus interface circuit and the image bus interface circuit and outputting the data to the change point detection circuit, whereby pattern data is input from the system bus interface circuit under control of the sequencer circuit. is input to the change point detection circuit via the first-in first-out memory, change point address information is output to the mode determination circuit, and the encoding mode information is input from the mode determination circuit to the system bus interface circuit via the data memory. It can also be used as a large-scale integrated circuit for converting and decoding image signals to output images. Under the control of the sequencer circuit, image restoration data information is input from the system bus interface circuit to the image restoration circuit via the data memory, and the restored image data is sent to the system bus interface via the data memory. It may also be a large-scale integrated circuit for encoding and decoding image signals output from the circuit. Further, an image signal code for controlling the sequencer circuit, inputting image restoration data information from the system bus interface circuit to the image restoration circuit via the data memory, and outputting the restored image data from the image bus interface circuit. It may also be a large-scale integrated circuit for encoding and decoding. Further, under the control of the sequencer circuit, change point address data is input from the system bus interface circuit to the mode determination circuit via the data memory, and the encoding mode is input from the system bus interface circuit via the data memory. The decoding mode information and change point address data are input from the system bus interface circuit to the mode determination circuit via the data memory, and the restored image data is sent to the system bus interface via the data memory. It may also be a large-scale integrated circuit for encoding and decoding image signals output from the circuit.

- Also, under the control of the sequencer circuit, change point address data and decoding mode information are input from the system bus interface circuit to the mode determination circuit via the data memory, and image restoration data is output to the image restoration circuit. However, the image signal encoding/decoding large-scale integrated circuit may output the image restored by the image restoration circuit from the system bus interface circuit via the data memory.

Effect 1) During encoding, an encoded line image signal is externally input to the image bus interface circuit, and during two-dimensional encoding, a reference line image signal is input to the image bus interface circuit and output to the change point detection circuit. The change point detection circuit inputs the encoded line image signal and the reference line image signal during two-dimensional encoding from the image bus interface circuit, outputs each change point address to the mode determination circuit, and also outputs the change point address of the encoded line. is output to a sequencer circuit, and during one-dimensional encoding, an encoded line image signal is input to generate color information and a change point address, the color information is output to a table search circuit, and a change point address is output to a sequencer circuit. During two-dimensional encoding, the mode determination circuit inputs the change point address of the encoded line and the change point address of the reference line, determines the encoding mode, and outputs the result to the table search circuit. The sequencer circuit controls each circuit, inputs the change point address, calculates the code run length of the encoded line using the arithmetic unit, and outputs the result to the chifur search circuit. The table search circuit inputs the encoding mode from the mode determination circuit and the code run length from the sequencer circuit during two-dimensional encoding, and inputs the color information from the change point detection circuit and the code run length from the sequencer circuit during one-dimensional encoding. and output code data to the system bus interface circuit. The system bus interface circuit outputs this code data to the outside.

2) During decoding, code data is externally input to the system bus interface circuit and output to the table search circuit. The table search circuit searches for the decoding mode and decoding run length during two-dimensional decoding based on this code data, outputs the decoding mode to the mode determination circuit, outputs the decoding run length to the sequencer circuit, and performs one-dimensional decoding. When converting, the color information and decoded run length are searched, the color information is output to the mode determination circuit, and the decoded run length is output to the sequencer circuit. The sequencer circuit controls each circuit, inputs the decoding run length, calculates address information using an arithmetic unit, and outputs the address information to the mode determination circuit. During two-dimensional decoding, the mode determination circuit inputs the decoding mode from the table search circuit, the address information of the decoded run length from the sequencer circuit, and the changing point address of the reference line image signal from the changing point detection circuit. During one-dimensional decoding, color information is input from the table search circuit, address information of the decoding run length is input from the sequencer circuit, and image restoration data is output to the image restoration circuit.

The image restoration circuit inputs the image restoration data and outputs the restored image signal to the image bus interface circuit.

During two-dimensional decoding, the change point detection circuit inputs the reference line image signal from the image bus interface circuit and outputs the change point address of the reference line to the mode determination circuit. The image bus interface circuit outputs the restored image signal to the outside.

3) Mode determination circuit and change point detection circuit test-1 Under the control of the sequencer circuit, pattern data is once input from the system bus interface circuit to the data memory of the sequencer circuit, and then output to the change point detection circuit. The change point detection circuit detects the change point and outputs change point address data to the mode determination circuit. The mode determination circuit determines the encoding mode, inputs it to the data memory, and then outputs it to the system bus interface circuit. In this way, the functions of the mode determination circuit and the change point detection circuit can be tested.

4) Mode judgment circuit, change point detection circuit test - 2 In addition to the circuit configuration of mode judgment circuit, change point detection circuit test - 1, data can be input from the system bus interface circuit and image bus interface circuit, and this data can be input. By providing a first-in, first-out memory for outputting to the change point detection circuit, pattern data is once input from the system bus interface circuit into the first-in, first-out memory and then input to the change point detection circuit under the control of the sequencer circuit. The change point detection circuit outputs change point address information to the mode determination circuit based on this pattern, and the mode determination circuit outputs the encoding mode to the data memory of the sequencer circuit. The functions of the mode determination circuit and the change point detection circuit are tested by outputting the encoding mode information from the data memory through the system main interface circuit.

5) Image restoration circuit test-1 Using the circuit configuration of mode determination circuit and change point detection circuit test-1, image restoration data is input from the system bus interface circuit to the data memory of the sequencer circuit, and then output to the image restoration circuit. The function of the image restoration circuit is tested by inputting the restored image data into the data memory again and outputting it from the system main interface circuit.

6) Image restoration circuit test-2 Using the circuit configuration of mode determination circuit and change point detection circuit test-1, image restoration data was input from the system bus interface circuit into the data memory of the sequencer circuit, and then output to the image restoration circuit. The function of the image restoration circuit is tested by outputting the restored image data from the image bus interface circuit.

7) Mode judgment circuit test Mode judgment circuit, change point detection circuit Using the circuit configuration of test-1, change point address data is input from the system bus interface circuit to the data memory of the sequencer circuit, and then output to the mode judgment circuit. After inputting this encoding mode to the data memory again, the system bus interface circuit outputs the decoding mode information and change point address data to the data memory of the sequencer circuit. After inputting the image data to the mode determination circuit, it generates restored image data, inputs the restored image data to the data memory again, and then outputs it from the system bus interface circuit.This allows the function of the controller circuit to be tested. .

8) Mode determination circuit, image restoration circuit test After inputting the change point address data and decoded moto information from the system bus interface circuit into the data memory of the sequencer circuit using the circuit configurations of the mode determination circuit and change point detection circuit test. , is input to a mode determination circuit to generate image restoration data and output to the image restoration circuit, and the image restored by the image restoration circuit is inputted again to the data memory and then output from the system bus interface circuit. This tests the functions of the mode determination circuit and image restoration circuit.

Embodiments Hereinafter, first to sixth embodiments of the present invention will be explained with reference to FIGS. 1 to 6.

FIG. 1 shows a CODEC LSI according to the first embodiment of the present invention.
This figure shows the schematic configuration of the . Its configuration consists of a system bus interface circuit 1 that is connected to an external microconverter, can input and output code data to and from this bus, and is equipped with a control register; When performing one-dimensional encoding, outputs encoded data based on color information and run length. During decoding, it searches the decoding table from encoded data, and when performing two-dimensional decoding, outputs encoded data based on color information and run length. A table search circuit 2 that outputs run length and outputs color information and run length during one-dimensional decoding, and a microprogram type circuit 3 that has an arithmetic function and controls the entire C0DEC-LSI, the details of which are explained in the sequencer. A sequencer address control circuit 3a that determines the address of the instruction code, a microprogram ROM 3b that stores the instruction code, an instruction register 3C3 that holds the instruction code for one cycle of the internal clock, a RAM 3d that is connected to the internal data bus 7, and an instruction A 7-enabler circuit 3 consisting of an arithmetic unit 3e that performs an operation specified by a code, a mode determination circuit 4a that detects the encoding method, an image restoration circuit 4b that generates a restored image, an encoded line image signal, and a reference line. A change point detection circuit 4c detects a change point from an image signal, and detects a change point and color information from an encoded line image signal during one-dimensional encoding. The image bus interface circuit 5 inputs and outputs signals and restored image signals. The operation of the image signal encoding/decoding large-scale integrated circuit configured as described above will be described below. In the sequencer circuit 3, the instruction code stored in the microprogram ROMab is sequentially output according to the address indicated by the sequencer address control circuit 3a, and is held in the instruction register 3c for one cycle of the internal clock. The sequencer address control circuit 3a normally increments the address every cycle of the internal clock, but an instruction code is input from the instruction register 3c, thereby performing an unconditional jump or a conditional jump. The jump address in this case is also specified by the instruction code. It's Kade.
If an address control block is provided in the sequencer address control circuit 3a, subroutines and roof operations can be performed. The arithmetic unit 3e performs arithmetic operations based on the instruction code, and transfers the results to the RAM 3d and each circuit via the internal data bus 7. The RAM 3d is also controlled by instruction codes and inputs and outputs data on the internal data bus 7. instruction register 3
The instruction code from c is outputted to each circuit through an internal control signal bus 6, and status signals and response signals from each circuit are inputted from the sequencer circuit 3 through this internal control signal bus 6 to perform overall control. Next, the operation of the entire circuit will be explained.

At the time of encoding, first, the control register in the system bus interface circuit 1 is set from the external CPU. As a result, the encoding program operates in the sequencer circuit 3, and requests the image bus interface circuit 5 to input the reference line image signal and the encoded line image signal (in the case of the MH encoding method, only the encoded line image signal). do. The input image signal is transferred to the change point detection circuit 4c, where the change point is detected, color information is also detected during one-dimensional encoding, and the change point address is output to the mode determination circuit 4a and the sequencer circuit 3. The mode determination circuit 4a determines the encoding mode and outputs it to the table search circuit 2. In the sequencer circuit 3, the change point address is subtracted by the arithmetic unit 3e.
By doing this, the run length is obtained and outputted to the table search circuit 2. In table search circuit 2,
When performing two-dimensional encoding, the encoding table is searched from the encoding mode and run-length information, and when one-dimensional encoding is performed, the encoding table is searched from the color information and run-length information, the encoded data is obtained, the bits of this encoded data are aligned, and the system bus Output to interface circuit 1.

Code data is output from here to the outside.

At the time of decoding, the control register in the system bus interface circuit I is similarly set from the external CPU, and the decoding program is thereby operated in the sequencer circuit 3. The code data is input to the table search circuit 2 through the system bus interface circuit 1. The table search circuit 2 searches a decoding table based on code data, determines the decoding mode and its run length during two-dimensional encoding, and determines color information and run length during one-dimensional decoding. The decoding mode and color information are determined by the mode determination circuit 4a.
The run length information is output to the sequencer circuit 3. In the sequencer circuit 3, the run lengths are added by the arithmetic unit 3C, and address information, which is the result of this arithmetic operation, is transferred to the mode determination circuit 4a. Also, during two-dimensional decoding, a reference line image signal is input from the image bus interface circuit 5, and this is transferred to the change point detection circuit 4C, where the change point of the reference line is detected and the change point address is It is output to the mode determination circuit 4a. The mode determination circuit 4a outputs the color (black or white), restoration start address, and end address of the restored image signal to the image restoration circuit 4b, and the image restoration circuit 4b sequentially restores images according to these instructions. The restored image signal is output to the outside through the image bus interface circuit 5.

When performing a chip test here, it is naturally possible to implement a method of actually inputting a pig and checking the encoded and decoded data output by the CODEC-LS and I. Furthermore, through the system bus interface circuit 1,
The pattern data is input to the RAM 3d in the sequencer circuit 3. In this case, the sequencer circuit 3 is controlled by using the RAM 3d instead of the reference line image signal and encoded line image signal input to the image bus interface circuit 5.
The data stored in is input to the change point detection circuit 4c.

The change point detection circuit 4c detects the change point of the input image signal and outputs change point address data to the mode determination circuit 4a. The mode determination circuit 4a determines the encoding mode based on this, and stores this encoding mode data in the RAM 3d within the sequencer circuit 3. When the operation from detecting a change point to determining the encoding mode for the pattern data previously input to the RAM 3d is completed, the encoding mode information data stored in the RAM 3d is outputted to the outside through the system bus interface circuit 1. Thereby, the function test of the mode determination circuit 4a and the change point detection circuit 4c can be performed from the system bus interface circuit 1.

FIG. 2 shows a CODEC LSI according to a second embodiment of the present invention.
The same reference numerals as in FIG. 1 indicate the same contents.

The difference between FIG. 1 and FIG. 2 is that a first-in, first-out memory is provided that can input data from the system bus interface circuit 1 and image bus interface circuit 5 and output this data to the change point detection circuit. The operation during decoding is only to transfer data from the image bus interface circuit 5 to the change point detection circuit 4C, and is the same as in the case of FIG. 1, so a description of the operation of the entire circuit will be omitted.

When performing a chip test, it is natural to implement a method of actually inputting data and checking the encoded and decoded data output by the CODEC-LSI. moreover,
Through the system bus interface circuit 1, the FIFO
Input data to the memory 4d. In this case, the control of the sequencer circuit 3 is to stop inputting the reference line image signal and encoded line image signal to the image bus interface circuit 5, and transfer the image data to the FIFO memory 4d. The image signal is not input from the interface circuit 5.The button data stored in the FIFO memo 'J4d is sequentially input to the change point detection circuit 4C, where the change point of this button data is detected and the mode is determined. circuit 4
The change point address is output to a. Mode determination circuit 4a
Now, the encoding mode is determined and this data is stored in the RAM 3d in the sequencer circuit 3. F in advance
When the encoding mode determination of the button data input to the IFO memory 4d is completed, the encoding mode information data stored in the RAM 3d is outputted to the outside through the system bus interface circuit 1.

FIFO Memo'J 4. If the capacity of d is small,
It is also possible to repeat the above operation several times.

Furthermore, when inputting pattern data to the FIFO memory 4d, it is also possible to store the pattern data in the RAM 3d and then transfer it to the FIFO memory 4d. This makes it possible to perform a functional test of the mode determination circuit 4as and the change point detection circuit 4c.

FIG. 3 shows a CODEC LSI according to a third embodiment of the present invention.
The same reference numerals as in FIG. 1 indicate the same contents. The difference between FIG. 1 and FIG. 3 is that data can be input and output from the internal data bus 7 to the image restoration circuit 4b.

The operations during encoding and decoding are the same as in FIG. 1, but the test method is different, so the test method will be explained. When performing a chip test here, it is naturally possible to implement a method of actually inputting data and checking the encoded and decoded data output by the LSI. Furthermore, through the system bus interface circuit 1, the sequencer circuit 3
The image restoration data information is stored in the RAM 3d inside. In this case, under the control of the sequencer circuit 3, the mode determination circuit 4
The image restoration circuit 4 uses the image restoration data information stored in the RAM 3d instead of the image restoration data information from a, that is, the start address, end address, and color information of the restored image.
Enter b. The image restoration port 4b restores the image according to this instruction, and stores the restored image data in the RAM 3d within the sequencer circuit 3. RAM3d in advance
When the image restoration for the image restoration data information inputted to is completed, the restored image data stored in the RAM 3d is outputted to the outside through the system bus interface circuit 1. This allows the function of the image restoration circuit 4b to be tested.

FIG. 4 shows a C0DEC LSI according to the fourth embodiment of the present invention.
The same reference numerals as in FIG. 1 indicate the same contents.

The difference between FIG. 1 and FIG. 4 is that data can be input from the internal data bus 7 to the image restoration circuit 4b.

The operations during encoding and decoding are the same as in the case of FIG. 1, but the test method for the image restoration circuit 4b is different, so this test method will be explained.

When performing a chip test here, it is naturally possible to implement a method of actually inputting data and checking the encoded and decoded data output by the LSI. Further, image restoration data information is stored in the RAM 3d in the sequencer circuit 3 through the system bus interface circuit 1. In this case, under the control of the sequencer circuit 3, instead of the image restoration data information from the mode determination circuit 4a, the RAM 3
The image restoration data information stored in d, that is, the start address, end address, and color information of the restored image are input to the image restoration circuit 4b. The image restoration circuit 4b restores the image according to this instruction, and outputs the restored image data to the outside through the image bus interface circuit 1. This allows the function of the image restoration circuit 4b to be tested.

FIG. 5 shows a CODEC LSI according to the fifth embodiment of the present invention.
The same reference numerals as in FIG. 1 indicate the same contents.

The difference from FIG. 1 is that data can be input/output from the internal data bus 7 to the mode determination circuit 4b, and an example of the detailed configuration of the mode determination circuit 4a during two-dimensional encoding and decoding is shown. It is.

The mode determination circuit 4a at the time of two-dimensional encoding and decoding includes an arithmetic unit 4al that performs an operation between a reference line image signal change point address and an encoded line image signal change point address, and determines the encoding mode from the result of this operation. Mode output circuit 4 that outputs
a2, an arithmetic unit 4a3 that calculates the address of the restored image from the decoded moto and reference line image signal change point address, and a multiplexer 4a4 that selects the output of the arithmetic unit 4a3 or the output from the sequencer circuit 3 as the address of the restored image. , mode determination circuit 4 according to instructions from sequencer circuit 3
The mode determination control circuit 4a5 controls the mode determination control circuit 4a5.

Next, the operation will be explained.

In the encoding operation, first, the control register in the system bus interface circuit 1 is set from the external CPU.

As a result, the encoding program operates in the sequencer circuit 3, and requests the image bus interface circuit 5 to input the reference line image signal and the encoded line image signal (in the case of the MH encoding method, only the encoded line image signal). do. Both input signals are transferred to the change point detection circuit 4c, where the change point is detected during dimensional encoding, and the change point address is output to the mode determination circuit 4a and the sequencer circuit 3. During one-dimensional encoding, changing points and color information are detected, changing point addresses are output to the sequencer circuit 3, and color information is output to the table search circuit 2. In the mode determination circuit 4a, the reference line image signal and the change point address of the encoded line image signal are input to the arithmetic unit 4al, and the two-dimensional encoding mode (bus mode, vertical mode, horizontal mode) is determined by comparing them. It is output from the output circuit 4a2 to the table search circuit 2.

In the sequencer circuit 3, the run length is obtained by subtracting the change point at l/s of the encoded line image signal using the arithmetic unit 3e, and this is output to the chifur search circuit 2. The table search circuit 2 searches the encoding table based on the encoding mode or color information and run length information, obtains encoded data, performs bit alignment on this encoded data, and outputs it to the system bus interface circuit 1.

Code data is output from here to the outside.

Similarly, the decoding operation is performed by setting the control register in the system bus interface circuit 1 from the external CPU, thereby causing the sequencer circuit 3 to operate the decoding program. The phase code data is inputted to the search circuit 2 through the system bus interface circuit 1. The table search circuit 2 searches the decoding table based on code data, determines the decoding mode and run length during two-dimensional decoding, and determines color information and run length during one-dimensional decoding. The decoding mode or color information is determined by the mode determination circuit 4a.
The run length information is output to the sequencer circuit 3. In the sequencer circuit 3, the run lengths are added together by the arithmetic unit 3e, and address information, which is the result of this arithmetic operation, is transferred to the mode determination circuit 4a. In addition, in the case of two-dimensional decoding mode, a reference line image signal is input from the image bus interface circuit 5, and this is input to the change point detection circuit 4.
Here, the change point of the reference line image signal is detected, and the change point address is output to the arithmetic unit 4a3 in the mode determination circuit 4a. The arithmetic unit 4a3 generates the address of the restored image from the decoding mode and the change point address of the reference line image signal.

In the multiplexer 4a4, in the case of one-dimensional decoding mode, the restored image address output from the sequencer circuit 3 is
In the case of two-dimensional decoding mode, the address of the restored image to be output from the arithmetic unit 4a3 is selected and output to the image restoration circuit 4b. The image restoration circuit 4b sequentially restores images according to this instruction.

The restored image signal is output to the outside through the image bus interface circuit 5.

When performing a chip test here, it is naturally possible to implement a method of actually inputting a pig and checking the encoded and decoded data output by the CODEC-LSI. Further, change point information data is input to the RAM 3d in the sequencer circuit 3 through the system bus interface circuit 1. In this case, under the control of the sequencer circuit 3, the RAM 3d is used instead of the output from the change point detection circuit 4c.
The data stored in is input to the mode determination circuit 4a. The mode determination circuit 4a determines the encoding mode from this,
This is stored in the RAM 3d in the sequencer circuit 3. When the encoding mode determination is completed for the change point address data previously input to the RAM 3d, the encoding mode data v stored in the RAM 3d is outputted to the outside through the system bus interface circuit 1. Further, decoding mode information and change point address data are input to the RAM 3d in the sequencer circuit through the system bus interface circuit 1. In this case, under the control of the sequencer circuit 3, the decoding mode information stored in the RAM 3d is input to the mode determination circuit 4a instead of the decoding mode output from the table search circuit 2, and the reference line is output from the change point detection circuit 4c. RAM instead of image signal change point address
The change point address stored in 3d is input to the mode determination section 4a. The mode determination circuit 4a generates the address of the restored image based on this, and stores it in the RAM in the sequencer circuit 3.
Store it in 3D. Thereafter, this data is similarly output to the outside. Thereby, the function of the mode determination circuit 4a can be tested.

FIG. 6 shows a C0DEC38 according to a sixth embodiment of the present invention.
-・The schematic structure of the LSI is shown, and the same reference numerals as in FIGS. 1 and 5 indicate the same contents. The difference from FIG. 5 is that data can be output from the image restoration circuit 4b to the internal data bus 7. The operations during encoding and decoding are the same as those in FIG. 5, so their explanation will be omitted.

When performing a chip test, it is naturally possible to implement a method of actually inputting data and checking the encoded and decoded data output by the CODEC-LSI. Further, change point address data and decoding mode information are input to the RAM 3d in the sequencer circuit 3 through the system bus interface circuit 1. In this case, under the control of the sequencer circuit 3, the change point address data stored in the RAM 3d is input to the mode determination circuit 4a instead of the reference line image signal change point address output from the change point circuit 6, and the change point address data from the table search circuit 2 is inputted to the mode determination circuit 4a. R instead of decoding mode output
The decoding mode information stored in AM3d is input to mode determination circuit 4a. The mode determination circuit 4a thereby generates an address for the restored image and outputs it to the image restoration circuit 4b. The image restoration circuit 4b generates a restored image from this information and stores it in the RAM 3d within the sequencer circuit 3.

When a certain operation is completed, the restored image data stored in the RAM 3d is transferred to the system bus interface circuit 1.
Output to the outside through. As a result, the mode determination circuit 4a
A functional test of the s-image restoration circuit 4b can be performed.

Effects of the Invention According to the present invention, a system bus interface circuit,
In a large-scale integrated circuit for image signal encoding and decoding, which consists of an image bus interface circuit, a table search circuit, a mode determination circuit, an image restoration circuit, a change point detection circuit, and a sequencer circuit, it is possible to test not only the entire Chinov, but also the mode determination circuit, It has the excellent effect that it is possible to test the image restoration circuit and the change point detection circuit individually or in combination, and to easily judge the quality of these functions alone or in combination.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the invention, FIG. 2 is a block diagram showing a second embodiment of the invention, FIG. 3 is a block diagram showing a third embodiment of the invention, and FIG. 4 is a block diagram showing a third embodiment of the invention. The figure is a block diagram showing a fourth embodiment of the present invention, FIG. 5 is a block diagram showing a fifth embodiment of the present invention, FIG. 6 is a block diagram showing a sixth embodiment of the present invention, and FIG. a) shows a terminating code, FIG. 7(b) shows a make-up code, FIG. 8 shows the positional relationship of change points in MR and MMR encoding systems, and FIG. 9 shows a two-dimensional code. FIG. 1°° System bus interface circuit, 2 Table search circuit, 3 Sequencer circuit, 3a Sequencer address control circuit, 3b... Micro program ROM
, 3c...Instruction register, 3d...RAM% 3
e. Arithmetic unit, 4a... Mode determination circuit, 4, al, 4a
3... Arithmetic unit, 4a2... Mode output circuit, 4a4
...M P・Internal control signal bus, 7
...Internal data bus. Name of agent: Patent attorney Shigetaka Awano and one other person” Tsuka-q

Claims (1)

[Claims] 1. A system bus interface circuit that inputs and outputs encoded data, and an image bus interface circuit that inputs and outputs encoded line image signals, reference line image signals during two-dimensional encoding, and restored image signals. During two-dimensional encoding, the change point address of the encoded line and the change point address of the reference line are input to determine the encoding mode and output, and during two-dimensional decoding, the address of the decoding mode and decoding run length is input. A mode determination circuit that inputs information, inputs a change point address of a reference line, inputs color information and decoded run length address information during one-dimensional decoding, and outputs image restoration data; An image restoration circuit that inputs and restores an image, and inputs an encoded line image signal and a reference line image signal during two-dimensional encoding, and determines the mode from the change point address of the encoded line and the change point address of the reference line. In addition to outputting it to the circuit, it also outputs the change point address of the encoded line. During one-dimensional encoding, the encoded line image signal is input and the color information and change point address are output, and during two-dimensional decoding, the reference line image is input. a change point detection circuit that inputs a signal and outputs a change point address of the reference line to the mode determination circuit; and a change point detection circuit that inputs the encoding mode and code run length of the encoded line during two-dimensional encoding; At the time of encoding, the color information and the code run length of the encoded line are input, and each code data is output to the system bus interface circuit, the code data is input from the system bus interface circuit, and at the time of two-dimensional decoding, the mode is It has a table search circuit that outputs the decoding mode and the decoded run length to the determination circuit, and outputs color information and the decoded run length during one-dimensional decoding, a data memory, and an arithmetic unit. During encoding, the change point address of the encoded line signal is input, the code run length of the encoded line is calculated and output to the table search circuit, and during one-dimensional and two-dimensional decoding, the decoded run length is input and the code run length of the encoded line is calculated and outputted to the table search circuit. a sequencer circuit that calculates the address information of the decoded run length and outputs it to the mode determination circuit and controls each of the circuits, and under the control of the sequencer circuit, pattern data is transferred from the system bus interface circuit to the data memory. input the change point address data to the change point detection circuit via the change point detection circuit, output the change point address data to the mode determination circuit, and output encoded mode data from the mode determination circuit to the system bus interface circuit via the data memory. A large-scale integrated circuit for image signal encoding and decoding. 2. A first-in, first-out memory is provided that inputs data from the system bus interface circuit and the image bus interface circuit and outputs the data to the change point detection circuit, and receives pattern data from the system bus interface circuit under the control of the sequencer circuit. Change point address information is input to the change point detection circuit via the first-in first-out memory and output to the mode determination circuit, and encoded mode information is input from the mode determination circuit to the system bus interface circuit via the data memory. 2. The large-scale image signal conversion/decoding integrated circuit according to claim 1, wherein the image signal conversion/decoding large-scale integrated circuit outputs an image signal. 3. Under the control of the sequencer circuit, image restoration data information is input from the system bus interface circuit to the image restoration circuit via the data memory, and the restored image data is sent to the system bus interface circuit via the data memory. 2. The large-scale integrated circuit for encoding and decoding image signals according to claim 1, wherein the image signal encoding/decoding large-scale integrated circuit outputs an image signal from the image signal encoding/decoding circuit. 4. Under the control of the sequencer circuit, image restoration data information is input from the system bus interface circuit to the image restoration circuit via the data memory, and the restored image data is output from the image bus interface circuit. 2. The large-scale integrated circuit for encoding and decoding image signals according to claim 1. 5. Under the control of the sequencer circuit, change point address data is input from the system bus interface circuit to the mode determination circuit via the data memory, and the encoding mode is input from the system bus interface circuit via the data memory. The decoding mode information and change point address data are input from the system bus interface circuit to the mode determination circuit via the data memory, and the restored image data is sent to the system bus interface via the data memory. 2. The large-scale integrated circuit for encoding and decoding image signals according to claim 1, wherein the image signal is output from the circuit. 6. Under the control of the sequencer circuit, input change point address data and decoding mode information from the system bus interface circuit to the mode determination circuit via the data memory, and output image restoration data to the image restoration circuit. 2. The image signal encoding/decoding large-scale integrated circuit according to claim 1, wherein the image restored by the image restoration circuit is outputted from the system bus interface circuit via the data memory.