JPH0244969A - Picture data processing unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The first aspect of the invention (industrial application field) The present invention is an image processing system that converts multivalued image data such as color image data and halftone image data into binary encoded image data. The present invention relates to a data processing device.

(Prior Art) Various methods have been considered for converting multivalued image data such as color image data and halftone image data into binary representation data for facsimile transmission, but some of them include bit-plane encoding. There is something called

This bit-plane encoding means that when each pixel data of a multilevel image is represented by n bits, each bit is handled as one image (bit-plane image) as shown in Figure 4, and A single multivalued image is expressed by a bit plane image. These n bit plane images are connected in the sub-scanning direction as shown in FIG. 5, and data is transmitted sequentially in units of bit plane images.

By the way, in facsimile transmission, it is inevitable that transmission errors will occur during transmission, and it is necessary to perform error correction on the receiving side. This error correction is performed, for example, by replacing all the lines in which errors have occurred with "white" or by replacing them with the data of the previous line.

However, the information contained in one line of the image shown in Fig. 5 is information of one arbitrary bit in each pixel, and n pieces of information located at the same coordinates of each bit plane image constitute the information of one pixel. It is possible that

Therefore, if only one line in which a transmission error has occurred is corrected by the above-described replacement, the information indicating one pixel may differ from the original information. That is, for example, in transmitting the image shown in FIG.
If a transmission error occurs in the Y1th line of [n-1] and all the image data of this line is replaced with rOJ, there will be no problem with the part where the original information is "0", but if the original information is "1" In that case, the information 11
The gradation of the pixel corresponding to -1. will be two times smaller.

In order to prevent such problems, it is necessary to correct all lines corresponding to the line in which the error has occurred, for example. Specifically, if a transmission error occurs on the Y1 line of plane [n-1], all Y1 lines from plane [0] to plane [n-21 corresponding to this line are error-corrected. Must.

However, in this case, it is necessary to perform line-to-line management for each bit-plane image, which is extremely troublesome. Furthermore, if a transmission error occurs in the line synchronization signal, the above-mentioned line-to-line management cannot be performed, making it difficult to reproduce the original image.

Therefore, image data is converted into HDLC frames and transmitted.
If a transmission error occurs, one possible method is to retransmit the frame in which the error occurred. However, this method requires complicated control and requires retransmission of one frame even if there is an error of only one bit, resulting in a longer transmission time.

(Problems to be Solved by the Invention) As mentioned above, in the past, bit plane images were connected in the sub-scanning direction and transmitted sequentially for each bit plane image, so correction of transmission errors was complicated. . Also, it has been considered that error correction can be omitted by performing data retransmission control, but there has been a problem in that it takes extra transmission time and the data transmission efficiency deteriorates.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an image data processing device that can obtain bit-plane n naturalized image data that can be easily corrected even if a transmission error occurs.

[Structure of the invention] (Means for solving the problem) As the concept is shown in FIG.
n storage means 1.2. each pixel data of a multivalued image made up of pixels is associated with each bit; ...1 in n
writing sequentially and in parallel over lines, ``n'' storage means 1, 2 . . . . When one line of pixel data is written to n, each of the storage means 1, 2, .・・・n to bi・
Each storage means 1, 2 . . . . It is characterized in that bit plane data for each line is obtained by serially reading data starting from n.

(Function) By taking such measures, even if a multivalued image is decomposed into bits, it is possible to obtain information on the same pixel line by line, which eliminates the complicated line-to-line management required in the past. This eliminates the need to perform error correction, and error correction becomes easier.

(Embodiment) An image data processing apparatus according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing the configuration when the same device is applied to a facsimile machine. Note that this embodiment exemplifies an image data processing apparatus that processes multivalued image data of 4 bits/pixel.

In Fig. 2, 10 is the main control section, 11 is the write control section, ]2
is a write address counter, 13 is a memory address switching section, 14a to 14d are buffer memories, 15 is a flip-flop, 16 is a readout control section, 17 is a readout address counter, 18 is a multi-value counter, and 19 is a multi-value selection section. . Further, 20 and 21 are external devices connected to this image data processing device, 20 is a multilevel image data generation unit, and 2] is a transmission encoding unit that performs redundancy suppression encoding such as MH encoding. be.

Next, the operation of the image processing apparatus configured as described in 1- above will be explained.

First, the main control section 10 outputs a write start signal S1 to the write control section 11, and outputs a multi-value image data output start signal S2 to the multi-value image data generation section 20. The main control unit 10 also includes a memory address switching unit 1
3, an address selection signal S3 is output. Then, the memory address switching unit 13 uses the write address S5 given from the write address counter 12 as the memory address S6 to each buffer memory 14a to 14d.
I can do it.

On the other hand, the main control unit 10 sends a multivalued image data output start signal S.
The multivalued image data generation unit 20 that received 2 is the write control unit 1.
] to request permission to output a multivalued image. Write control section 1
1 outputs a data output permission signal to the multi-valued image data generating section 20 to permit output of multi-valued image data upon receiving this data output permission request signal S7, and writes data to the write address counter 12. Output pulse S4. This write pulse S4 is applied to the buffer memory 14a~
]-4d is also manually inputted as a clock pulse.

By the way, the multi-valued image data generating section 20 outputs the multi-valued image data S9 when receiving the data output permission signal S8 from the write control section 11. The multivalued image data S9 is input to a 4-bit flip-flop]5, latched by a data output permission signal S8, and sent to each buffer memory 14a to 1.
．． 4d to each bit of information S10a-S1.
Od is output in parallel. buffer memory], 4
Bit information S 10 a -S 10 d input from flip-flops]-5 are respectively stored in storage areas designated by memory address S6 in synchronization with write pulse S4.

According to the procedure described in ``2'' below, one line of multivalued image data is divided into bits and stored in buffer memories 1, 4 a to 14.
It is stored in d. Then, bit information S of multivalued image data for one line 1. Oa~S 1. When writing to buffer memories 1.4a to 14d of Od is completed,
The write address counter 2 outputs a write end signal Sll to the main control unit 10. The main control unit 10 receives the write end signals 31, 1, stops outputting the write start signal S1 and the multivalued image data output start signal S2, and ends the write. Thereafter, the memory address switching unit 13 is switched by the address selection signal S3, and the read address S12 output from the read address counter 7a is set as the memory address S6 to each buffer memory 1.4a to 14.
Give to d. Further, the main control section 10 outputs a read start signal 813 to the read control section 16 and outputs a transmission encoding start signal S14 to the transmission encoding section 21.

Here, when the read control unit 16 receives the read start signal 813 from the main control unit 10, the read address counter 7
And a read pulse 515 is output to each buffer memory 1.4a to 14d.

The buffer memories 14a to 1.4d use this read pulse S15 as a clock pulse to output data in the storage area specified by the memory address S6.

The output data S]6a to S1.6d of the buffer memories 14a to 14d are input to one multivalue selection section, one of which is selected and applied to the readout control section 16. It will be done.

By the way, the buffer memory 1 created by this one multi-value selection section
The selection of output data 516a to 516d of 4a to 14d is performed as follows. That is, at the start of reading, the multi-value selection section 19 selects the output data S16 of the buffer memory 14a. In this state, data is output from each buffer memory 148 to 14d, and when data output for one line is completed, read address counter 17 outputs one line read end signal 51.7 to multivalue counter 18. do. When the multi-value counter 18 receives this one-line read end signal S17, it outputs a switching selection symbol S18 to one multi-value selection section. When the switching selection signal 318 is input, one multi-value selection unit selects the next output data S 6 b of the buffer memory 14b. Thereafter, in the same manner, the buffer memories 14c, 1
．． 4d are selected in sequence.

The serial data S19 sequentially selected by the multi-value selection unit 19 and given to the readout control unit 16 is sent to the transmission encoder 21 along with the transfer lock S20 and the line synchronization signal S21.
The signal is output to the transmission encoder 21 and encoded to suppress redundancy.

Then, in a state where the output S]6d of the multi-value selection unit 19 or the buffer memory 14d is selected, when the one-line read end signal S]7 from the read address counter 17 is given to the multi-value counter]8, the multi-value The counter 18 outputs a read end signal S22 to the main control unit 10. When the main control unit 10 receives this read end signal S22, it stops the read start signal 813 and the 91 encoding start signal S14, and ends the read.

As shown in FIG. 3, the image data is read out line by line, as if a plurality of bit plane images were consecutively arranged in the line direction. The above process is repeated for each line. As a result, bit-plane encoded image data of focus information of the same pixel or existing on the same line as shown in FIG. 3 is obtained.

In this way, according to this embodiment, it is possible to obtain bit-plane encoded image data that exists on the same line L or the pixel information of the same pixel. As a result, regarding the correction of transmission errors in bit-plane encoded image data, since the signal correlation between each line is maintained, the replacement etc. generally used in facsimile machines can be applied as is, and it is extremely This makes it possible to easily correct errors.

Note that the present invention is not limited to the above embodiments.

For example, in the embodiment described in "-", an example was given in which processing multi-valued image data in which one pixel is represented by 4 bits.
The present invention is not limited to processing bit/picture multi-value image data.

In addition, various modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] According to the present invention, each pixel data of a multivalued image consisting of n bits/pixel is stored in n storage means provided in association with each bit, sequentially and parallelly for one line. write to, -1
- When one line of pixel data is written to the n storage means, -1- the one line of bit plane data, which is divided into bits and stored in each of the n storage means, is sequentially serialized from each storage means. By reading to line jli
Therefore, even if a transmission error occurs, it is possible to obtain bi-sotoprene n-encoded image data that can be easily corrected.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the concept of the present invention, FIGS. 2 and 3 are diagrams explaining an image data processing device in an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of the device. ,
Fig. 3 is a diagram showing an image obtained with the apparatus shown in Fig. 2;
5 and 5 are diagrams for explaining the prior art. 10... Main control unit, 11... Write control unit, 12.
-Write address counter, 13...Memory address la converter, 14a to 14d...Buffer memory, 15
. . . flip-flop, ] 6 . . . readout control unit, 1
7... Read address counter, 18... Multi-value counter, 19... Multi-value selection section. Applicant's agent Patent attorney Takepi Suzue Figure 5

Claims (1)

[Claims] means for sequentially and parallelly writing each pixel data of a multivalued image consisting of n bits/pixel into n storage means provided in association with each bit over one line; and the n storage means When pixel data for one line is written in the means, means is provided for sequentially and serially reading out one line's worth of bit plane data stored in each of the storage means by dividing the bits into bits from each storage means. An image data processing device characterized by: