JPH03192972A - Picture reader - Google Patents

Abstract

PURPOSE:To execute high-speed bit plane encoding by reading out multilevel picture data by every bit plane directly from a memory in which the multilevel picture data is stored. CONSTITUTION:A picture data input part 16 reads a picture as multilevel data, and a bit plane memory 17 for the multilevel picture data is constituted so es to store successively the multilevel data by a picture element unit at the time of data input, and output the picture data by every plane number at the time of data output. Then, an encoding part 18 encodes the picture data stored in the bit plane memory 17 for the multilevel picture data by every bit plane, and an interface part 19 sends the data encoded by the encoding part 18 to a host computer. Thus, the high-speed bit plane encoding can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an image reading device that reads and encodes an image including halftones, such as a photograph, as multi-tone data.

"Prior Art" For example, when a facsimile machine transmits a document containing halftones, such as a color photograph, the document is read as multivalued image data, encoded, and transmitted. Since multi-value image data requires a huge amount of data to be transmitted compared to binary images, various encoding methods have been considered to compress multi-value image data and transmit it efficiently. .

As a method for efficiently encoding such multivalued image data, there is a method of managing each image in units of gradation planes (bit-branes) and encoding each bit-brane.

FIG. 11 shows the concept of conventional bit-brain encoding.

In the case of 2N gradation multivalued image data expressed by N bits, the memory is configured with N bit planes from the 0th plane to the N-1th plane corresponding to each bit of the multivalued image data. Each bit of multivalued image data is sequentially stored pixel by pixel in a corresponding bit plane. Since the stored data is binary data for each bit brain, the encoding used in facsimile machines can be applied as is.

The gradation of multivalued image data such as a color photograph is generally the same across multiple pixels or changes gradually, so the number of bits by which the value of binary data changes compared to the previous pixel. There are few. Therefore, when looking at the binary data of each bit brain, "O" or "l" are likely to be consecutive. Therefore, even when performing one-dimensional run-length encoding, for example, it becomes possible to encode efficiently.

``Problems to be Solved by the Invention'' In this way, bit-brain encoding stores, for example, multi-valued image data read for one line in a memory, and reads and encodes it bit-brane by bit-brain.

However, conventionally, multivalued image data has been written in a memory pixel by pixel and read out pixel by pixel. For example, when encoding the first bit brain, all pixels are read out sequentially, and the first bit data for each pixel is controlled by a CPU (central processing unit) or by using a shift register. Take it out. next,
When encoding the i+1th pip lane, all pixels are read out sequentially again and the i+1th bit information is extracted.

That is, when reading multivalued image data from a memory for encoding, it is necessary to read out the same pixel for each bit brain. Therefore, in order to encode a bit plane consisting of N gradations and n pixels, it is necessary to read the memory NXn times, which has the disadvantage of slowing down the bit plane encoding processing time.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an image reading device capable of high-speed bit-brain encoding.

"Means for Solving the Problems" The image reading device of the present invention includes (i) image data input means for scanning a document pixel by pixel and inputting multivalued image data;
11) A plurality of bit memories in which multi-value image data is written bit by bit are conceptually arranged in a matrix, and a bit plane memory stores at least one line of multi-value image data, and (iii) from an image data input means. a writing means for writing multivalued image data input pixel by pixel into each row of the bit plane memory; The image reading apparatus includes a reading means and (V) an encoding means for encoding data read by the reading means.

That is, the present invention is configured such that the memory in which multivalued image data is stored can be accessed (read) based on the beep/) plane number, rather than on a per-pixel basis.

"Example" Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 1 shows an outline of an image reading device according to an embodiment of the present invention.

A CPU (central processing unit) 11 of this image reading device is connected to the following units through a path 12 such as a data bus, and is configured to perform various controls.

The ROM 13 is a read-only memory that stores a program for controlling the overall operation of the apparatus, such as reading and encoding multivalued image data.

RAM 14 is a random access memory that stores data for various controls.

The image data input unit 16 is for reading an image as multivalued data, and includes an optical system, a motor, etc. (not shown). In this embodiment, it is assumed that the multivalued image data consists of 8 bits per 1 pixel, and the number of pixels in 1 line is n.

The bit plane memory 17 for multivalued image data is configured to sequentially store multivalued data pixel by pixel when inputting data, and output image data for each brane number when outputting data. The input/output data width to the memory 17 is 8 bits.

The encoding unit 18 encodes the image data stored in the multilevel image data bit plane memory 17 for each bit plane. As the encoding method, run-length encoding, two-dimensional encoding, etc. are possible, but the present invention is not limited to these methods.

The interface unit 19 is used, for example, to exchange control information with the host computer and to transmit data encoded by the encoding 1ffl18 to the host computer.

FIG. 2 shows the configuration of a bit memory that constitutes a bit plane memory for multivalued images.

The bit memory 21 includes an address designation terminal 23 connected to an address bus 22, and an address to be written or read bit by bit is designated via the address bus 22. The write signal terminal 24 is connected to the control bus 26, and the read signal terminal 27 is connected to the control bus 28, and these terminals 24 and 27 are both active low.

The output terminal of a two-input gate element 31 is connected to the chip select terminal 29 of the bit memory 21 . A pixel select bus 32 is connected to one input terminal of the gate element 31, and a plane select bus 33 is connected to the other input terminal. These select buses 32.
33 is normally supplied with a high (H) level select signal. When a low level select signal is supplied from one of the select buses, a low level signal is output from the gate element 31 and the chip select terminal 29 becomes active.

Data input/output terminal of bit memory 21 (D>34,
A bit input bus 37 is connected via a bit input gate 36. The bit input gate 36 is active low, and when supplied with a low (L) level control signal, passes the bit data supplied through the bit input bus 37. A bit output bus 39 is also connected to the data input/output terminal 31 via a bit output gate 38. The bit output gate 38 is active low and allows bit data to pass through the bit output bus 39 when a low level control signal is supplied.

FIG. 3 shows the configuration of the storage section of the bit plane memory for multivalued images.

The storage unit 41 includes 64 bit memories 21.

These 64 bit memories 21 have 8 columns in order to store each bit of one pixel consisting of 8 bits in this embodiment, and 8 columns in order to read out in units of 8 bits.
arranged in rows.

The 0th line of the bit memory 21 is the bit memory 21-0 ~
A common pixel select bus 32-0 is connected to one input terminal of each gate element 31. Similarly, each of the eight bit memories 2 in the first row
A common pixel select bus 32-1 to 32-7 is connected to one input terminal of the gate element 31 of each of the eight bit memories 21 in the 1st to 7th rows.

The 0th column of the 64 bit memories 21 is a bit memory.
Mori 2 1-7, 21-15,...
..., 21-55, 21-63, and a common plane select bus 33-0 is connected to the other input terminal of each gate element 31. Similarly, the other input terminals of the gate elements 31 of the eight bit memories 21 in the first column to the eight bit memories 21 in the seventh column are connected to common plane select buses 33, respectively.
-1 to 33-7 are connected.

The data input/output terminals 34 of each bit memory IJ 21 are connected via bit output gates 38 to bit output buses 39-0 to 39-7 common to each row. Further, the data input/output terminal 34 is connected to a common bit input bus 37-0 to 37-3 for each column via each bit input gate 36.
7-7.

FIG. 4 shows the configuration of the select section of the bit plane memory for multivalued images.

The selection unit 42 includes an address selector 43, a plane selector 44, a pixel selector 46, a first data buffer 47, and a second data buffer 48. The address selector 43 includes an input terminal A and an input terminal B, each of which is connected to a different bus of the address bus 49.

The output terminal Y of the address selector 43 is connected to the address bus 2.
2, and when a low level signal is input to the select terminal, the input from input terminal A is output, and when a high level signal is supplied, the input from input terminal B is output. .

The plane selector 44 has three input terminals connected to the address bus 49. Brain selector 44
When a low-level signal is supplied from the select terminal, a low-level control signal is output from the output terminal based on the signal supplied from each input terminal. The plane selector 44 is one of the plane select buses 33-7 to 33-0.
These are selected one after another and a low level signal for one line is output for each.

The pixel selector 46 includes three input terminals connected to the address bus 49. Bixel selector 46
When the signal from the select terminal color low level health is supplied, it selects one of the pixel select buses 32-D to 33-7 for each pixel based on the signal supplied from the input terminal and outputs a low level signal. It is supposed to be done.

When the first data buffer 47 is supplied with a low level signal from the select terminal, each column (
3) is supplied to the data bus 51 via the bit output buses 39-7 to 39-0. When the second data buffer 48 is supplied with a low level signal from the select terminal, the data bus 51
The bit input buses 37-θ to 37-7 connected to the bit memory 21 of each row receive pixel-by-pixel information supplied through the
It is designed to output to .

A control bus 52 for controlling data writing or reading is connected to the select section 42 . The control bus 52 is connected to select terminals of the address selector 43, pixel selector 46, and second data buffer 48. The control bus 52 connects the brain selector 44 and the first data buffer 47 via an inverting gate 53.
is connected to the select terminal.

Next, the operation of writing and reading data in the multivalued image bit plane memory 17, which is composed of the storage section 41 and the selection section 42, will be explained.

Writing multivalued image data Multivalued image data is written to the bitplane memory 17 for multivalued images.
When writing to the control bus 26 of the storage unit 41 (FIG. 3)
A low level write signal is supplied to . A low-level write signal is supplied to each write signal terminal 24, and the bit memories 21-O to 21-63 become writable. Further, a low-level control signal is supplied from the control bus 52, and the bit input gate 36 connected to the data output terminal 34 of each bit memory 21 becomes open.

On the other hand, when a low level control signal is supplied from the control bus 52, the pixel selector 46 and the second data buffer 48 become active (FIG. 4). The pixel selector 46 selects a pixel select bus 32-0 based on a signal supplied from the address bus 49 for each pixel.
to pixel select bus 32-7.
l (J fm No. 48 is output repeatedly for one line in sequence.

Now, the low level control signal is on the pixel select bus 3.
It is assumed that the output is 2-0. The low level control signal is supplied to gate elements 31-0 to 31-7 connected to pixel select bus 32-0 (FIG. 3). Low level signals are output from these gate elements 31-0 to 31-7, and bit memories 21-0 to 21-7 are selected. As a result, the multivalued image data in units of pixels supplied from the data bus 51 is transmitted bit by bit from each bit input bus 37 to the selected bit memory 21-0 to 21-7 via the bit input gate 36 in the open state. are written respectively. Writing to each bit memory 21 is performed at a designated address based on an address designation signal supplied from the address bus 22 via the address selector 43.

When writing for one pixel is completed, a low-level control signal (") is output to the pixel select bus 32-1, and the bit memo 'J21-8~21-
Multivalued image data of the next pixel is written in 15. 0th
The lines from the 7th line to the 7th line are written to the same address. From pixel select bus 32-〇 to gate element 31-
When the low-level control signals are sequentially outputted up to 7, the address selector 43 outputs an address designation signal that designates the next address to the address bus 22.

Reading of multi-value image data When reading multi-value image data written in the multi-value image bit plane memory 17, the storage unit 410 control bus 2
8 is supplied with a low level read signal. A low level read signal is supplied to each read signal terminal 27, and the bit memories 21-0 to 21-63 become readable.

Further, a high-level control signal is supplied from the control bus 52, and the bit output gate 38 connected to the data input/output terminal 34 of each bit memory 21 becomes open.

On the other hand, when a high level control signal is supplied from the control bus 52, it is inverted by the inverting gate 53, and the plane selector 44 and first data buffer 47 become active (FIG. 4). The plane selector 44 sequentially outputs low-level control signals from the brain select bus 33-0 to the plane select bus 33-7 based on the address designation signal supplied from the address bus 49.

Now, the low level control signal is on the brain select bus 3.
3-7, the gate elements 31-0.31-8, . . . , 31 connected to this
A low level signal is output from -49.31-56. As a result, the bit memories 21-0, .
..., 21-56 is selected, and the address bus 22
Each piece of data written to the address specified by the signal supplied from is read out one bit at a time. Subsequently, data for one line is read from the bit memory 21 in the seventh column. The data read from each bit memory 21 is supplied to the first data buffer 47 via the bit output gate 38 and the bit output bus 39, respectively.
It is output from the data bus 51.

When the reading of one line from the bit memory 21 in the seventh column is completed, the pixel select buses 32-6, 36-5, . . . , 3
Low level signals are output for one line in the order of 6-0.

Next, such a multivalued image bit plane memory 17
The operation of bit-plane encoding of multivalued image data using is explained below.

FIG. 5 shows the structure of one line of multivalued image data read by the image data input section.

The image data input unit 16 sequentially reads pixels from the 0th pixel to the nth pixel for each line, and supplies multivalued image data for each pixel. In this embodiment, data is read out in units of 8 bits, so blocks are divided into units of 8 pixels.

FIG. 6 shows the flow of encoding multivalued image data supplied from the image data input section.

The CPU 11 initializes a memory pointer that specifies an address at which writing of multi-value image data is started in the multi-value image bit plane memory 17 (step 2). C
The PUII receives one pixel worth of multivalued image data from the image data input section 16 (step ■), and writes it to the specified address of the bit memory 21 in the specified row through the pixel select bus 32 (FIG. 3). (Step ■)
.

FIG. 7 shows the data bit structure when writing multi-value image data to the multi-value image bit plane memory. Each bit of each pixel is supplied to a corresponding bit input bus 37-θ to 37-7, and written into a predetermined bit memory 21.

After writing one pixel worth of multivalued image data, the CPU II increments the memory pointer (step ■).

If the writing of each pixel for l lines has not been completed, skip step (2); N) and return to step (2) to repeat the process. When writing for one line is completed, CP
UII is “7” as the number of the plane to read
(Step ■) and initializes the memory pointer (Step ■). The CPU II sets each bit memory 21 (
3), a total of 1 byte of data of 1 bit at a time is read out (step 2).

FIG. 8 shows the bit configuration of data read out from the multivalued image bit plane memory. One byte of data read one bit at a time from each of the eight bit memories 21 in the column corresponding to the set plane is output via bit output buses 39-7 to 39-0.

CPLIII increments the memory pointer (step ■), and the read data is stored in the encoder 1.
8 (step [F]) and encoded.

One line for the plane with the set number (8197
If the reading for 7 minutes) is not completed (step ■; N), the process returns to step ■ and the reading is repeated. 1
When reading for a line is completed (step ■; Y)
, decrements the set plane number (step 0).

If the CPU II has not finished reading all the planes (step 0; N), it returns to step (2) and repeats the reading for each plane. When reading is completed for all the branes, in step @; Y), writing for each pixel and reading for each plane for one line of multivalued image data is completed. If not completed for all lines, skip step (2); return to step (2) and repeat writing for each pixel and reading for each plane for the next line. If writing and reading have been completed for all lines, skip step @;
Y), the process ends.

FIG. 9 shows a memory map in which one line of multi-value image data has been written in the multi-value image bit plane memory. The symbol X in the figure is the address set in step (2).

However, the addresses are different from the addresses for each bit memory 21.

FIG. 10 shows a memory map when reading one line of multi-value image data from the multi-value image bit plane memory. The symbol X in the figure represents the step ■
This is the address set in , and is different from the address for each bit memory 21.

In the embodiment described above, multi-value image data is written and read line by line, but multi-value image bit plane memory is used for multiple lines, for example, one page, and multi-value image data is written. It is also possible to perform the read processing and the read processing separately.

Furthermore, in the embodiment described above, the multivalued image data supplied from the image data input section is written as is into the bitplane memory for multivalued images, and bitplane encoding is performed based on this data. It is also possible to take a difference from the multivalued image data of , and bit-brain encode the value.

"Effects of the Invention" As described above, according to the present invention, since the configuration is such that each bit plane is directly read from the memory in which multilevel image data is stored, it is possible to perform high-speed bit brain encoding. Become. Moreover, efficient encoding can be performed by bit-brain encoding multivalued image data.

[Brief explanation of drawings]

1 to 10 are for explaining one embodiment of the present invention, of which FIG. 1 is a block diagram showing the circuit configuration of an image reading device, FIG. 2 is a circuit diagram of a bit memory, Figure 3 is a circuit diagram of the storage section of the bit plane memory for multi-level images, Figure 4 is a circuit diagram of the select section of the bit plane memory for multi-level images, and Figure 5 is the multi-level image read by the image data input section. Explanatory diagram showing the configuration of one line of data, No. 6
The figure is a flowchart showing the flow of writing and reading multi-value image data, Fig. 7 is an explanatory diagram of the data bit structure of the writing poem of multi-value image data, and Fig. 8 is the data bit structure of reading multi-value image data. An explanatory diagram of the configuration, FIG. 9 is an explanatory diagram showing a memory map when writing to memory, FIG. 10 is an explanatory diagram showing a memory map when reading memory, and FIG. 11 is a conceptual diagram for explaining the concept of bit plane memory. It is. 11...CPU, 16...Image data input unit, 17...Bit plane memory for multivalued image, 18...Encoding unit.

Claims (1)

[Scope of Claims] Image data input means for scanning a document pixel by pixel and inputting multi-value image data, and a plurality of bit memories for writing multi-value image data bit by bit, arranged in a matrix, and for at least one line. a bit plane memory for storing multivalued image data for each pixel; a writing means for writing the multivalued image data input pixel by pixel from the image data input means for each row of the bitplane memory; An image reading device comprising: reading means for reading data written in each row in the bit plane memory for each column; and encoding means for encoding data read by the reading means. .