JPH0245372B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge transfer device (CTD), such as a BBD.
The present invention relates to an output circuit.

The BBD is generally configured as shown in FIG.
In the figure, an input terminal 1 is connected to the base of an npn type transistor 2, the emitter of this transistor 2 is grounded through a constant current source 3, and the collector is connected to a power supply terminal 4. This transistor 2
The emitter of the capacitor C ₀ is connected to one end of the capacitor C ₀ through the reverse diode 5.
It is connected to the clock terminal 6 through. Also, one end of the capacitor C ₀ is connected to the emitter of an npn transistor Q ₁ , the collector of this transistor Q ₁ is connected to the emitter of the next stage npn transistor _{Q 2 ,} and so on. Q ₃
The collector and emitter of . . . are connected in sequence, and the collector of the final stage transistor is connected to the power supply terminal 4. Capacitors C ₁ and C ₁ are connected between the collector and base of these transistors Q ₁ , Q 2 , respectively.
C ₂ ... is connected. Note that capacitors C ₁ , C ₂ …
The capacitance values of ... are all equal to the capacitor C ₀ and are set as C. In addition, the suffix is an odd number of transistors.
The bases of Q ₁ , Q ₃ , . . . are connected to the clock signal generation circuit 8 through the clock terminal 7, and the bases of the transistors Q ₂ , Q ₄ .

The clock terminals 6 and 7 each have a second
As shown in Figures A and B, clock signals φ ₁ and φ ₂ are supplied which have potentials of V _DC and V _DC +V _P , have a duty ratio of 50%, and have opposite polarities. Note that the voltage V _P is the power supply voltage V _CC supplied to the power supply terminal 4.
For that, V _CC > V _DC + 2V _P.

Furthermore, it is supplied to input terminal 1. The voltage V _S of the input signal is in the range of V _DC +V _P ≦V _S ≦V _DC +2V _P.

In this device, in the initial state, the capacitor
All terminal voltages of C ₀ , C ₁ , and so on are charged to V _P . Furthermore, when the voltage V _S at the input terminal is divided into a DC component V _SDC and an AC component V _SAC , only the AC component V _SAC is 0 in the initial state.

Therefore, in the initial state, the hot end side of capacitors C ₀ , C ₂ . . . with an even number of suffixes is
As shown in Figure 2C, during the period of V _DC +V _P , the signal φ ₁ once rises to V _DC +2V _P and then becomes V _SDC ,
During the period when the signal φ ₂ is V _DC +V _P , it once drops to V _SDC −V _P and then becomes V _DC +V _P. In addition _, as shown in Fig _. 2D, the hot end side of capacitors _{C 1} , _{C 3 .} V _DC +V _P
Then, during the period when the signal φ ₂ is V _DC +V _P , it once becomes V _DC +
After rising to 2V _P , it becomes V _SDC .

Then, during the period when the first signal φ ₁ is V _DC +V _P immediately after the input signal is supplied, if the voltage of the input signal at this time is V _S = V _S1 , the potential on the hot end side of the capacitor C ₀ is temporarily set to V _DC After rising to +2V _P , it becomes V _S1 . That is, the capacitor C ₀ is discharged and stores the charge of {V _S1 −(V _DC +V _P )}C. At this time, transistor _Q1 is off, so the capacitor
There is no change in C ₁ , C ₂ ....

Next, during the period when the following signal φ ₂ is V _DC +V _P ,
First, the potential of signal _φ1 becomes V _DC , so the capacitor
The potential on the hot end side of _C0 is V _S1 − (V _DC + V _P ) +
V _DC =V _S1 −V _P. Then, since the transistor Q ₁ is turned on, the potential on the hot end side of the capacitor C ₀ eventually rises to the base potential (V _DC +V _P ) of the transistor Q ₁ . At this time, transistor Q ₁ is operating in the active region, so charging of capacitor C ₀ is as follows: terminal 7 → capacitor C ₁ → collector/emitter of transistor Q ₁ → capacitor C ₀
This is done through the following route. Then, the potential on the hot end side of capacitor C ₀ changes from V _S1 -V _P to V _DC +V _P , so the transfer of charge from the hot end side of capacitor C ₁ to the hot end side of capacitor C ₀ is as follows: {(V _DC +V _P )−V _S1 −V _P )}C=(V _DC +2V _P −V _S1 )C. On the other hand, since the capacitor _C1 initially stored a charge of V _P・C, the final charge amount of the capacitor _C1 is V _P・C−(V _DC +2V _P −V _S1 )C={V _S1 − (V _DC +V _P )}C. In other words, if the capacitor C ₀ was at V _S1 − (V _DC + V _P ) during the period when the signal φ ₁ was at V _DC + V _P ,
Signal φ ₂ moves to capacitor C ₁ during V _DC +V _P , and capacitor C ₀ returns to V _DC +V _P. Note that since transistor Q ₂ is off, capacitors C ₂ and C ₃
There is no change in...

Furthermore, in the period when the next signal φ ₁ is V _DC +V _P , if the input signal voltage is V _S = V _S2 , capacitor C ₀ is charged to V _S2 − (V DC + V P ), and capacitor C ₁ is charged to V S2 − (V _DC + V _P ). V _DC +V _P and capacitor C ₂ is returned to V _S1 −
It is charged to (V _DC +V _P ). Note that transistor Q ₃
Since is off, capacitor _C3 and subsequent capacitors do not change.

The above operation is repeated, and the signal is moved from left to right in the drawing in synchronization with the signals φ ₁ and φ ₂ .

In such a device, for example, the transfer function H _(z) H _(z) = 0.5Z ^-1 −0.5Z ^-2 However, Z ^-1 = e ^-s 〓 s = jω = j2πf f is the frequency of the input signal τ = When 1/f _c f _c constitutes an acyclic transversal filter having a so-called comb-shaped characteristic of the clock frequency, the applicant of the present application previously proposed the following circuit.

That is, in FIG. 3, capacitor C _o ,
C _o+3 (n is an even number) is divided into C _o ′,
C _o ″, C _o+3 ′, and C _o+3 ″, and their capacitance values are 0.5C. The cold end side of the other divided capacitor C _o ″ is connected to the terminal 6 , and the cold end side of the other divided capacitor C _o+3 ″ is connected to the terminal 7 .

Also, complementary transistor 11,
The twelve emitters are connected together and this connection point is connected to the cold end of the capacitor C _o '. Further, the bases of transistors 11 and 12 are connected to each other, and this connection point is connected to generation circuit 8 through terminal 6'. From this generation circuit 8, a signal φ _{1 '} which has the same phase as the signal φ 1 and takes the potentials of V _DC −V _BE and V _DC +V _P +V _BE (where V _BE is the voltage between the base and emitter of the transistor) is sent to the terminal ₆ . ’. The collector of the npn transistor 11 is connected to the power supply terminal 4, and the collector of the pnp transistor 12 is connected to the current mirror circuit _M1.
It is connected to the collector and base of the input side npn type transistor 13 that constitutes
No. 3 emitter is grounded. The base of an npn type transistor 14 on the output side constituting the current mirror circuit _M1 is connected to the base of the transistor 13, and the emitter of the transistor 14 is grounded.

More complementary transistor 1
The 5 and 16 emitters are connected to each other, and this connection point is connected to the cold end of the capacitor C _o+3 '. Further, the bases of transistors 15 and 16 are connected to each other, and this connection point is connected to generation circuit 8 through terminal 7'. This generating circuit 8 supplies a signal φ _{2 '} which has the same phase as the signal φ 2 and takes the potentials of V _DC −V _BE and V _DC +V _P +V _BE . Then, the collector of the pnp transistor 16 is grounded, and the npn
The collector of the type transistor 15 is connected to the collector and base of a PNP type transistor 17 on the input side constituting the current mirror circuit M ₂ , and the emitter of the transistor 17 is connected to the power supply terminal 4 . The base of the output side PNP type transistor 18 constituting the current mirror circuit M ₂ is connected to the base of the transistor 17 , and the emitter of the transistor 18 is connected to the power supply terminal 4 .

A second BBD (BBDb) is also provided to which the DC component V _SDC of the input signal V _S is supplied to its input terminal 1b. The collectors of the transistors 14 and 18 described above are connected, and this connection point is connected to the hot end side of the capacitor _Cb1 constituting BBDb.

In this circuit, when no input signal is supplied, all terminal voltages of the capacitor are at V _P.

On the other hand, in the period when the signal φ ₁ is V _DC +V _P immediately after the input signal is supplied, if the voltage of the signal supplied during this period is V _S = V _S1 , then the capacitor
The terminal voltage of _C0 is changed from V _P to V _S1 − (V _DC + V _P ). Furthermore, after _{0.5τ , the terminal voltage of capacitor C 0 changes} from V _S1 −V _P to (V _DC
+V _P ).

Then, during the period when the signal φ ₂ after n+1/2τ is V _DC +V _P , the terminal voltages of both capacitors Cn' and Cn'' are changed from V _S1 −V _P to (V _DC +V _P ), and during this period, the terminal voltage of capacitors Cn' A charge of 0.5C (V _S1 −V _P ) −0.5 C (V _DC +V _P ) = 0.5 C {(V _DC +2V _P )−V _S1 } is discharged through the collector of the transistor 12 .

Furthermore, during the period when the signal φ ₂ is V _DC +V _P after n+3/2τ, the capacitor C _o+3 ' is discharged, and the discharged charge at this time is 0.5CV _P −0.5C{V _S1 −(V _DC +V _P )}=0.5C{(V _DC +2V _P )−V _S1 }, and this charge is discharged through the collector of the transistor 15.

These discharged charges are inverted by current mirror circuits M ₁ and M ₂ respectively, extracted and injected from capacitor Cb ₁ , and thereby
The transfer function H (z) from the hot end side (tap T ₁ ) of Cn', Cn'' to the hot end side (tap T ₂ ) of capacitor Cb ₂ is H _{( z)} = 0.5Z ^-1 -0.5Z ^-2. .

However, in this circuit, since complementary transistors 11, 12, 15, and 16 are provided in the signal extraction portions, the number of elements increases and power consumption also increases. This was a problem especially when converting the circuit into an IC.

In view of these points, the present invention is designed to enable a plurality of output signals to be obtained with a simple configuration. An embodiment of the present invention will be described below with reference to the drawings.

In Figure 4, the cold end of capacitor Cn′ is complementary transistor 2.
Connected to emitters 1 and 22. The bases of these transistors 21 and 22 are connected to terminal 6'.
The collector of the npn type transistor 21 is connected to the collector and base of the input side pnp type transistor 23 constituting the current mirror circuit _M3 , and the emitter of the transistor 23 is connected to the power supply terminal 4.
connected to. The base of the output side pnp type transistor ₂₄ constituting this current mirror circuit M3 is connected to the base of the transistor 23, the emitter of the transistor 24 is connected to the power supply terminal 4, and the collector is connected to the hot end side of the capacitor _Cb0 . be done.

Furthermore, the collector of the pnp transistor 22 is the npn on the input side that constitutes the current mirror circuit _M4 .
The emitter of the transistor 25 is grounded. The base of the output side npn type transistor ₂₆ constituting this current mirror circuit M4 is connected to the base of the transistor 25, and the transistor 2
The emitter of 6 is grounded and the collector is a capacitor.
Connected to the hot end side of Cb ₃ .

In this circuit, the terminal voltage of capacitors Cn' and Cn'' changes from V P to V _S1 - (V _DC + V _{P )} during the period when the signal φ ₁ is V _DC + V _P after n/2τ after the input signal is _supplied .
During this time, a charge of 0.5C {V _DC +2V _P )-V _S1 } is discharged from the capacitor Cn' through the collector of the transistor 21. This charge is inverted by current mirror circuit _M3 and injected into capacitor _Cb0 .

Also, during the period when the signal φ ₂ after n+1/2τ after the input signal is supplied is V _DC +V _P , the capacitor Cn′,
The terminal voltage of Cn'' is changed from V _S1 −V _P to V _DC +V _P , and during this time, a charge of 0.5C {(V _DC +2V _P )−V _S1 } is discharged from the capacitor Cn′ through the collector of the transistor 22. .This charge is inverted by current mirror circuit _M4 and extracted from capacitor _Cb3 .

And in this circuit, at the time when the signal related to the signal V _S1 is extracted from the capacitor Cb ₃ , the signal injected into the capacitor Cb ₀ is transferred to the capacitor Cb ₁
and after another 1τ the capacitor Cb ₃
will be forwarded to. In other words, the signal injected into capacitor Cb ₀ is transferred to capacitor Cb ₃ .
It is transmitted with a delay of 1τ from the signal extracted from Cb ₃ .

Therefore, in this circuit, the transfer function H _(z) from tap T ₁ to the hot end side (tap T ₂ ') of capacitor Cb ₄ is H _(z) = 0.5Z ^-1 -. 5Z ^-2 , and a filter with the same comb-shaped characteristics as described above is formed.

In this way, the output is taken out from the BBD, and according to the present invention, two output signals are taken out from the pair of complementary transistors 21 and 22, which reduces the number of elements and reduces power consumption.

In particular, the present invention can reduce the number of complementary transistors by half when forming a large-scale filter device, and can significantly reduce power consumption, which is effective when converting the circuit into an IC.

Furthermore, FIG. 5 shows a case where the present invention is applied to a general acyclic transversal filter.

In the figure, the cold end of capacitor C _o+1 is disconnected from terminal 7, and this capacitor C _o+1
The cold end sides of the transistors 21 and 22 are connected to the emitters of the transistors 21 and 22, and the bases of the transistors 21 and 22 are connected to the terminal 7'.

At the same time, a resistor 27 with a resistance value RX is connected to the emitter of the transistor 23 of the current mirror circuit _M3 .
will be provided. Further, two transistors [24 ₁ , 24 ₅ ] are provided on the output side of the current mirror circuit M ₃ , and the bases of these transistors 24 ₁ , 24 ₅ are connected to the base of the transistor 23 . Furthermore, resistors 28 ₁ and 28 with resistance values R ₁ and R ₅ are connected to the emitters of these transistors 24 ₁ and 24 ₅ , respectively.
₅ is provided. and these transistors 2
The collectors of 4 ₁ and 24 5 are capacitors Cb _{1 and} 24 ₅ , respectively.
Connected to the hot end side of Cb ₅ .

Also, transistor 2 of current mirror circuit _M4
A resistor 29 having a resistance value R _Y is provided at the emitter 5. Further, two transistors [26 ₄ , 26 ₈ ] are provided on the output side of the current mirror circuit M ₄ , and the bases of these transistors 26 ₄ and 26 ₈ are connected to the base of the transistor 25 . Furthermore, resistors 30 ₄ and 30 ₈ having resistance values R ₄ and R ₈ are provided at the emitters of these transistors 26 ₄ and 26 ₈ , respectively. And these transistors 26 ₄ , 2
The collectors of 6 _{and 8} are connected to the hot end sides of capacitors Cb ₄ and Cb ₈ , respectively.

Further, the cold end side of the capacitor Cb ₀ is disconnected from the terminal 6, the cold end side of the capacitor Cb ₀ is connected to the emitters of complementary transistors 31 and 32, and the bases of the transistors 31 and 32 are connected to the terminal 6'.

The collector of the pnp type transistor 32 is connected to the collector and base of the input side transistor 35 constituting the current mirror circuit _M6 .
The emitter of this transistor 35 is grounded through a resistor 39 having a resistance value R _X '. There are two transistors on the output side of this current mirror circuit _M6 [3
6 ₁ , 36 ₅ ] are provided, and these transistors 3
The bases of 6 ₁ and 36 ₅ are connected to the base of transistor 35 . Furthermore, these transistors 36
The emitters ₁ and ₃₆₅ are grounded through resistors ₄₀₁ and ₄₀₅ having resistance values _R1 ' and _R5 ', respectively. Here, it is assumed that R _X ′/R ₁ ′=R _X /R ₁ and R _X ′/R ₅ ′=R _X /R ₅ . And these transistors 36 ₁ , 3
The collectors of 6 ₅ are connected to the hot end sides of capacitors Cb ₁ and Cb ₅ , respectively.

Further, the collector of the npn type transistor 31 is connected to the collector and base of the input side transistor 33 constituting the current mirror circuit _M5 , and the emitter of this transistor 33 has a resistance value of
It is connected to the power supply terminal 4 through the resistor 37 of R _Y '. Two transistors [34 ₄ , 34 ₈ ] are provided on the output side of the current mirror circuit M ₅ , and the bases of these transistors 34 ₄ , 34 ₈ are connected to the base of the transistor 33 . Furthermore, the emitters of these transistors 34 ₄ and 34 ₈ are connected to the power supply terminal 4 through resistors 38 ₄ and 38 ₈ having resistance values R ₄ ′ and R ₈ ′, respectively. Here, it is assumed that R _Y ′/R ₄ ′=R _Y /R ₄ and R _Y ′/R ₈ ′=R _Y /R ₈ . And these transistors 34 ₄ , 3
The collectors of 4 _{and 8} are connected to the hot end sides of capacitors Cb ₄ and Cb ₈ , respectively.

In this circuit, any signal φ ₂ changes from the terminal voltage of capacitor Cn V _DC +2V _P during the period of V _DC +V _P.
When the voltage changes to V _S , a charge amount X of (V _DC +2V _P -V _S )C=X is passed through the collector of the transistor 21 during this period.

This amount of charge X is the transistor 23 and resistor 2
7. Charges R _X /R ₁ (=a ₁ ) and R _X /R ₅ (=a ₅ ) times the amount of charge X flowing through the transistor 23 are then passed through the transistors 24 ₁ , 24 ₅ and the resistors 28 ₁ , 28 ₅ , respectively. be swept away. Therefore, these charges are injected into each capacitor C ₁ and C ₅ .

When the terminal voltage of the capacitor Cn changes from V _S −V P to V _DC +V _P during the period when the subsequent signal φ ₁ is V _DC +V _P , the charge of (V _DC +2V _P −V _S )C= _X during this period A quantity X is passed through the collector of transistor 22.

This amount of charge X is the transistor 25 and the resistor 2
It flows through 9. Charges R _x /R ₄ (=a ₄ ) and R _x /R ₈ (=a ₈ ) times the amount of charge X flowing through the transistor 25 flow through the transistors 26 ₄ and 26 ₈ and the resistors 30 ₄ and 30 ₈ , respectively. be swept away. Therefore, these charges are extracted from each capacitor C ₄ and C ₈ .

The signals resulting from these injections and extractions are transferred in synchronization with the clock signals φ ₁ and φ ₂ ,
Based on the time when the signal V _S flows through the transistor 21, the signal injected into the capacitor Cb ₁ after 4τ is transferred to the capacitor Cb ₉ , and the signal extracted from the capacitor Cb ₄ after 3τ is transferred to the capacitor Cb. transferred to ₉ and capacitor after 2τ
The signal caused by being injected into _Cb5 is sent to the capacitor
Cb ₉ , and after 1τ the signal extracted from capacitor Cb ₈ is transferred to capacitor Cb ₉ .

That is, in this circuit, the signals flowing through the transistor 21 are connected to the capacitor Cb ₉ at −a ₁ , a ₄ ,
Weighted by −a ₅ and a ₈ , a composite signal of 4τ delay, 3τ delay, 2τ delay, and delayed signals is obtained, respectively.
As a result, the transfer function H _(z ) from the hot end side (tap T ₃ ) of capacitor Cn ₊₁ to the hot end side (tap T ₄ ) of capacitor Cb ₉ is H _(z) = (a ₈ − _{a 5} Z ^{− 1} +a ₄ Z ^-2 −a ₁ Z ^-3 )Z ^-1 .

Furthermore, at BBDb, during the period when signal φ ₂ is V _DC +V _P , the terminal voltage of capacitor Cb ₀ changes from V _SDC −V _P.
When the voltage changes to V _DC +V _P , the amount of charge X _DC (V _DC +2V _P -V _SDC )C=X _DC is passed through the collector of the transistor 32 during this period.

This amount of charge X _DC is passed through transistor 35 and resistor 39. and transistor 35
The charges flowing through _{the transistors} 36 ₁ and 36 ₅ and the resistors 40 ₁ and 40 are R _{X ′} /R _{1 ′} (=a ₁ ), R Flowed through ₅ .

Therefore, these charges are extracted from each capacitor Cb ₁ and Cb ₅ . Here, this extracted charge is the DC component of the signal weighted by a ₁ and a ₅ , and
From the above transistors 24 ₁ , 24 ₅ to the capacitor
This corresponds to the DC component of the signal charge injected into Cb ₁ and Cb ₅ .

Similarly, during the period when the signal φ ₁ is V _DC +V _P ,
When the terminal voltage of the capacitor Cb ₀ changes from V _DC +2V _P to V _SDC , the amount of charge X _DC of (V _DC +2V _P -V _SDC )C=X _DC is passed through the collector of the transistor 31 during this period.

This amount of charge X _DC is passed through the transistor 33 and the resistor 37. and transistor 33
The _charges flowing through the _{transistors 34 4 , 34 8} and _the resistors 38 _{4 ,} 38 are R Streamed through ₈ .

Therefore, these charges are extracted from each capacitor Cb ₄ and Cb ₈ . Here, this extracted charge is the DC component of the signal weighted by a ₄ and a ₈ , and is
A capacitor is connected to the transistors 26 ₄ and 26 ₈ described above.
This corresponds to the DC component of the signal charge extracted from Cb ₄ and Cb ₈ .

Therefore, in this circuit, the transistors 24 ₁ ,
The DC component V _SDC of the signal charge injected and extracted at 24 ₅ , 26 ₄ , 26 ₈ is canceled out, and the capacitor Cb ₁
~Cb ₈ is injected with only the AC component V _SAC .

In this way, an acyclic transversal filter is formed, and according to the present invention, only two pairs of complementary transistors are required.
The number of elements is reduced and power consumption is also reduced.

Furthermore, FIG. 6 shows a case where a cyclic transversal filter is constructed. In the figure, the cold end side of capacitor _C8 is transistor 21,
This transistor 2 is connected to the emitter of 22.
1 and 22 are connected to the terminal 6', and
Current mirror circuit M ₃ is transistor 24 ₂ , 2
The capacitors C ₁ and C ₅ are connected through transistors 26 ₁ and 26 ₅ of the current mirror circuit M ₄ to the hot end sides of the capacitors C ₂ and C ₆ through 4 ₆ .
connected to the hot end side of the Also capacitor
The cold end side of Cb ₁ is transistor 31,3
This transistor 3 is connected to the emitter of 2.
1 and 32 are connected to terminal 7', and
Transistor 36 ₂ , 3 of current mirror circuit M ₆
The capacitors C _{1 and C 5 are connected to the hot end sides of the capacitors C 2 and} C ₆ through the transistors _{34 1} and 34 ₅ of the current mirror circuit M _{6 .}
connected to the hot end side of the Others are the same as in FIG.

Therefore, in this circuit, the charges detected from the capacitor C ₈ are weighted by the current mirror circuits M ₃ , M ₄ , and this charge is transferred to the capacitors C ₁ , C ₂ ,
At the same time, the DC component of each charge is injected from the current mirror circuit M ₅ , _{M 6 ,} and only the AC component is injected into each capacitor C _{1 ,} C ₂ , C ₅ , C ₆ . is extracted and injected.

In this circuit, the transfer function H _(z) from the hot end side of capacitor C ₀ to the hot end side of capacitor C ₈ is R _X /R ₁ = R _X ′R ₁ ′=a ₁ , R _X ′/R ₂ =R _{X ′ / R 2} ′ ₌ a ₂ , _R
Assuming ^{that R} _{X / R 6 = R _} ^_ _{_} ^_ _{_} ^_ . Note that the other functions and effects are the same as those shown in FIG.

Note that the present invention is applicable not only to BBD but also to CCD.

Furthermore, since the core of the technical idea of this application is to obtain a pair of outputs from complementary transistors to which a clock is supplied, this technical idea applies not only to transversal filters but also to output circuits of charge transfer elements such as delay circuits. It is obvious that this can also be applied.

[Brief explanation of drawings]

Figures 1 and 2 are diagrams for explaining the BBD, Figure 3 is a diagram for explaining the conventional device, Figure 4 is a connection diagram of an example of the present invention, and Figures 5 and 6 are diagrams for explaining the conventional device. It is a block diagram of another example. 1 is an input terminal, 21 and 22 are complementary transistors, and M ₃ and M ₄ are current mirror circuits.

Claims (1)

[Claims] 1. A signal having the same phase as the clock signal of the charge transfer element is commonly supplied to the control terminals of a pair of complementary active elements, the controlled terminals of the pair of active elements are connected to each other, and this connection point is connected to the charge transfer element. An output circuit for a charge transfer element, which is connected to a cold end side of a capacitor of the transfer element, and obtains an output current from each of the output electrodes of the pair of active elements.