JPH0245423B2 - TANRAKUYORYOYOKUSEISOCHI - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a short-circuit capacity suppression device that performs power interchange between power systems.

[Prior art]

FIG. 1 shows a conventional short circuit capacitance suppressing device. In the figure, 1 is the first power system, 2 is the second power system, and 3 is a short-circuit capacity suppression device that interconnects both power systems 1 and 2, and is configured for each phase of A, B, and C. ing. 4a, 4b, 4c and 5a, 5b, 5c are input/output terminals between each power system 1, 2 and the short-circuit capacity suppressing device 3. Note that the A phase, B phase, and C phase are functionally equivalent. Therefore, the following explanation will be made only regarding the A phase. 6 and 7 are thyristors connected in antiparallel, and are composed of a plurality of thyristors. 8 is a series reactor that suppresses the peak value of fault current;
The value has been selected so that it does not interfere with the interconnection effect. A voltage detector 9 includes a voltage transformer that detects the voltage applied to the thyristors 6 and 7, and outputs a voltage signal 10.
11 is a current detector consisting of a current transformer that detects the interconnection current; 12 is a current value discriminator that receives the current signal 13 from the current detector 11 and determines the level of the interconnection current; Accident detection signal 14
issue. Reference numeral 15 denotes a gate signal generator which generates gate signals P ₁ and P ₂ in synchronization with the voltage signal 10 when there is no accident detection signal 14, and stops the gate signals P ₁ and P ₂ when the accident detection signal 14 is received. V _a1 , V _b1 and V _c1
is the voltage between each phase of A, B, and C on the first power system 1 side and the ground. V _a2 , V _b2 , and V _c2 are voltages between each phase of A, B, and C on the second power system 2 side and the ground.

In the above configuration, when both power systems 1 and 2 are in a normal interconnected state where no fault has occurred, the voltages of both power systems 1 and 2 are almost the same, and there is no large difference in phase. Furthermore, since the gate signal generator 15 always generates the gate signals P ₁ and P ₂ , the thyristor 6,
7, one of them is always conductive. Therefore, the two power systems 1 and 2 are interconnected via the impedance of the reactor 8, and since the voltage and phase difference between the two power systems 1 and 2 are not large, the interconnection current is below the specified value. . This situation is shown in Figure 2 a~
Shown in d. That is, FIG. 2a shows the voltages V _a1 and V _a2 between each terminal of the thyristors 6 and 7 and the ground. Figure 2b shows the voltage difference between the thyristors 6 and 7.
A gate signal _P1 to the thyristor 6 is issued when the voltage phase, which is the voltage applied to the
The current flows through the thyristor 6 for a period of 180°.
Thyristor 7 receives gate signal _P2 with a delay of 180° from thyristor 6, and is also energized for a period of 180°. This operation is repeated one after another, and a continuous current flows as shown in FIG. 2c as the interconnection current, and this value is less than the specified value. In addition, Fig. 2 d
Also shown are gate signals P ₃ , P ₄ , P ₅ and P ₆ for the B and C phases other than the A phase.

Next, consider a case where an accident such as a ground fault or short circuit of a power transmission line occurs in the second power system 2. As the voltage of the second power system 2 drops due to the accident, a large voltage difference occurs between the two power systems 1 and 2, and the fault current flows from the first power system 1 to the second power system 2. . This is not desirable considering the responsibility of the circuit breaker to eliminate faults, as it increases the fault current (that is, increases the short circuit capacity) by interconnecting both power systems 1 and 2. do not have. Therefore, as soon as an accident occurs, all gate signals to the thyristors 6 and 7 of the short-circuit capacity suppressing device are stopped and brought into a non-conducting state, so that the fault current flowing from the first power system 1 to the second power system 2 can be immediately stopped. Can be blocked. Therefore, although the circuit breaker for accident recovery in the second power system 2 is connected to the first power system 1 under normal conditions, it is not connected to the first power system 1. It would be a good idea to have a duty to disconnect without considering interconnection.

By the way, in what has been explained so far, when the voltage and phase between both power systems 1 and 2 are approximately equal in a normal interconnected state, the voltage V _a1 −V _a2 applied to the thyristor becomes almost zero; In reality, there is voltage distortion included in both power systems 1 and 2, so the fundamental wave voltage component becomes smaller.
Harmonic voltage components that cannot be canceled out become more prominent. This situation is shown in FIGS. 3a to 3d. In other words, as shown in Figure 3a, when the voltages between the two power systems 1 and 2 almost match, including magnitude and phase, as the fundamental wave component, which was the main component of the differential voltage, becomes smaller, the remaining Harmonic components become noticeable. In an extreme case, only the harmonic voltage is applied to the thyristors 6 and 7 as shown in FIG. 3b, and the interconnection current i _a shown in FIG. 3c flows.

In such a state, the number of gate signals to the thyristors 6 and 7 increases as shown in Fig. 3d, so especially when the thyristors 6 and 7 are light-direct firing thyristors, the light emitting element It has a big impact on lifespan. Furthermore, since the detection voltage is small and contains a large amount of harmonics, the phase of the ignition signal cannot be accurately determined, leading to irregular ignition, which can result in the generation of even more harmonic current. There is sex.

[Summary of the invention]

The present invention has been made in view of the above, and includes a first signal that is issued when the difference in voltage between both power systems is greater than or equal to a predetermined value, and a first signal that is issued when the difference in voltage between both power systems is greater than or equal to a predetermined value. and the inverted signal of the second signal issued when
By configuring to issue a thyristor firing permission signal when the AND condition is met, the thyristor will not fire when the voltage difference between the two power systems is lower than a predetermined value, thereby reducing harmonic current. To provide a short circuit capacity suppressing device capable of preventing the occurrence of short circuits.

[Embodiments of the invention]

The figures will be explained below. In Figure 4,
1 to 14 are the same as the conventional ones. Reference numeral 16 denotes a voltage level discriminator that monitors the voltage signal 10, and when a fundamental voltage higher than that expected to cause the harmonics generated between both power systems 1 and 2 to be below a predetermined value is detected, the voltage level is detected. Issue signal 17. 18 inputs the inverted signal of the accident detection signal 14 and the voltage level detection signal 17, and outputs the firing permission signal 19 of the thyristors 6 and 7 when the AND condition of the inverted signal and the voltage level detection signal 17 is satisfied. . Reference numeral 20 denotes a gate signal generator which, upon receiving the ignition permission signal 19, outputs ignition signals P ₁ and P 2 alternately to the thyristors 6 and 7, respectively, at around 90° of the differential voltage between the two power systems 1 and ₂ ; Gate signal when there is no ignition permission signal 19
Do not emit P ₁ or P ₂ .

According to the above configuration, the voltage between the input and output terminals 4a and 5a is larger than the specified value, and both power systems 1,
When there is no fault in power supply system 2, gate signals P ₁ and P ₂ are output alternately in synchronization with the power supply frequency, so both power systems 1 and 2 remain interconnected via reactor 8. .

On the other hand, if the voltage between the input/output terminals 4a and 5a is smaller than the specified value, the voltage level detection signal 17 is not output, so the gate signal of the thyristors 6 and 7 is
P ₁ and P ₂ do not appear.

In the above embodiment, the voltage level discriminator 16 can use a conventional comparator. Alternatively, it may be configured by software using a microcomputer.

In the above embodiments, the interconnection between two different power systems has been described, but the present invention can also be applied to bus interconnection within the same system.

〔Effect of the invention〕

According to this invention, the first signal is output when the voltage difference between interconnected power systems is equal to or greater than a predetermined value, and the second signal is output when the interconnection current is equal to or greater than a predetermined value.
When the AND condition with the inverted signal of the signal is satisfied,
By configuring the system to issue a firing permission signal for the thyristor that connects both power systems, the thyristor will not fire when the voltage difference between the two power systems is smaller than a predetermined value. The generation of wave voltage can be suppressed.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram showing a conventional short-circuit capacity suppression device, Figure 2 is an explanatory diagram showing the waveforms of Figure 1 during normal operation, and Figure 3 is a diagram of harmonic voltage and current in the configuration of Figure 1. An explanatory diagram showing the situation, FIG. 4 is a configuration diagram showing an embodiment of the present invention. In the figure, 1 is the first power system, 2 is the second power system, 6 and 7 are thyristors, 9 is a voltage detector, 11 is a current detector, 12 is a current value discriminator, 1
4 is an accident detection signal (second signal), 16 is a voltage level discriminator, 17 is a voltage level detection signal (first signal), 20 is 19 is an ignition permission signal, and 20 is a gate signal generator. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (1)

[Claims] 1. In a device that interconnects a first power system and a second power system with thyristors connected in antiparallel to provide power interchange, the voltage across the thyristors is detected by a voltage detector, and the voltage difference is detected. When is above a predetermined value, the voltage level discriminator outputs a first signal, the interconnection current between the two power systems is detected by a current detector, and when the current is above a predetermined value, the current value discriminator outputs a first signal. A short-circuit capacitor characterized in that a second signal is output, and when an AND condition of the first signal and an inverted signal of the second signal is established, a gate signal generator outputs an firing permission signal for the thyristor. Suppressor.