JPH0245438B2 - - Google Patents

Info

Publication number
JPH0245438B2
JPH0245438B2 JP57197369A JP19736982A JPH0245438B2 JP H0245438 B2 JPH0245438 B2 JP H0245438B2 JP 57197369 A JP57197369 A JP 57197369A JP 19736982 A JP19736982 A JP 19736982A JP H0245438 B2 JPH0245438 B2 JP H0245438B2
Authority
JP
Japan
Prior art keywords
frequency
load
output
control element
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57197369A
Other languages
Japanese (ja)
Other versions
JPS5986481A (en
Inventor
Satoshi Hamada
Yoshiaki Komuro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sansha Electric Manufacturing Co Ltd
Original Assignee
Sansha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sansha Electric Manufacturing Co Ltd filed Critical Sansha Electric Manufacturing Co Ltd
Priority to JP57197369A priority Critical patent/JPS5986481A/en
Publication of JPS5986481A publication Critical patent/JPS5986481A/en
Publication of JPH0245438B2 publication Critical patent/JPH0245438B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Description

【発明の詳細な説明】 この発明は、高周波インバータの制御素子に電
界効果トランジスタを用いて振動性負荷に高周波
出力を供給する高周波電源装置の制御方法に関
し、負荷を流れる出力電流の位相を出力電圧の位
相より常に遅れ位相に制御し、制御素子の内部に
派生するダイオードの逆回復電流による制御素子
の破壊を防止するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for controlling a high-frequency power supply device that supplies a high-frequency output to a vibrating load by using a field-effect transistor as a control element of a high-frequency inverter. This is to prevent destruction of the control element due to the reverse recovery current of the diode derived inside the control element.

一般に、フエライト振動子等を振動させる超音
波発振器や誘導加熱器などには、高周波インバー
タで構成された高周波電源装置が設けられ、前記
インバータの出力側には、インダクタンス成分お
よび該成分との整合を計るためのコンデンサ成分
の共振回路からなる振動性負荷が接続される。
Generally, an ultrasonic oscillator or an induction heater that vibrates a ferrite vibrator or the like is equipped with a high-frequency power supply device composed of a high-frequency inverter, and an inductance component and a matching component with the inductance component are installed on the output side of the inverter. An oscillatory load consisting of a resonant circuit of capacitor components for measurement is connected.

そして高周波インバータにより負荷を直列共振
する場合、負荷のばらつきや負荷変動により、高
周波インバータの出力周波数と、負荷の共振周波
数とが異なると、高周波インバータの出力電力は
負荷に効果的に供給されなくなり、また、高周波
インバータにより負荷を並列共振する場合、高周
波インバータに過大電流が流れるため、該インバ
ータの容量を大きくする必要がある。
When a high-frequency inverter causes a load to resonate in series, if the output frequency of the high-frequency inverter differs from the resonant frequency of the load due to load variations or load fluctuations, the output power of the high-frequency inverter will not be effectively supplied to the load. Furthermore, when a high-frequency inverter causes a load to resonate in parallel, an excessive current flows through the high-frequency inverter, so it is necessary to increase the capacity of the inverter.

ところで、高周波電源装置の高周波インバータ
には、制御素子としてトランジスタなどの半導体
素子が用いられ、制御素子に電界効果トランジス
タを用いたハーフブリツジ形の高周波インバータ
は、第1図に示すように、SIPMOS型の電界効
果トランジスタ(以下FETと称する)からなる
第1,第2制御素子Q1,Q2の直列回路が第
1,第2直流電源E1,E2の直列回路に接続さ
れるとともに、両電源E1,E2の接続点、すな
わち電源E1の陰極と電源E2の陽極との接続点
であるa点と、両制御素子Q1,Q2の接続点、
すなわち制御素子Q1のソースと制御素子Q2の
ドレインとの接続点であるb点との間に、インダ
クタンス成分Lxと容量成分Cyの並列回路を有す
る負荷Zと、突入電流防止用のリアクトルLyと
が直列に接続されている。
By the way, the high-frequency inverter of a high-frequency power supply uses a semiconductor element such as a transistor as a control element, and a half-bridge type high-frequency inverter using a field effect transistor as a control element is a SIPMOS type high-frequency inverter as shown in Fig. 1. A series circuit of first and second control elements Q1 and Q2 consisting of field effect transistors (hereinafter referred to as FETs) is connected to a series circuit of first and second DC power supplies E1 and E2, and a series circuit of both power supplies E1 and E2. A connection point, that is, a point a, which is a connection point between the cathode of the power source E1 and the anode of the power source E2, and a connection point between both control elements Q1 and Q2,
That is, a load Z having a parallel circuit of an inductance component Lx and a capacitance component Cy, and a reactor Ly for inrush current prevention are connected between point b, which is the connection point between the source of the control element Q1 and the drain of the control element Q2. connected in series.

なお、制御素子Q1のドレインが電源E1の陽
極に接続されるとともに、制御素子Q2のソース
が電源E2の陰極に接続されている。
Note that the drain of the control element Q1 is connected to the anode of the power source E1, and the source of the control element Q2 is connected to the cathode of the power source E2.

そして制御素子Q1のゲートに接続された第1
制御端子I1と、制御素子Q2のゲートに接続さ
れた第2制御端子I2とに、交互に制御信号が入
力され、両制御素子Q1,Q2がスイツチング
し、負荷Zに高周波電力が供給される。
and a first one connected to the gate of control element Q1.
Control signals are alternately input to the control terminal I1 and the second control terminal I2 connected to the gate of the control element Q2, both control elements Q1 and Q2 are switched, and high frequency power is supplied to the load Z.

しかし、制御素子Q1のドレイン,ソース間
に、ドレインからソースに流れる順方向電流に対
して逆極性になる第1内部逆ダイオードD1が、
順方向電流の大きさに従つて派生するとともに、
制御素子Q2のドレイン,ソース間にも、ダイオ
ードD1と同様の第2内部逆ダイオードD2が派
生する。
However, between the drain and source of the control element Q1, there is a first internal reverse diode D1 which has a polarity opposite to the forward current flowing from the drain to the source.
It is derived according to the magnitude of the forward current, and
A second internal reverse diode D2 similar to the diode D1 is also derived between the drain and source of the control element Q2.

そして第2図a,bに示すように、両制御端子
I1,I2に、所定パルス幅の制御信号が交互に
入力される場合、ta時〜ta′時の制御信号により
制御素子Q1がオンした後、tb時〜tb′時の制御
信号により制御素子Q2がオンし、さらに、tc時
〜tc′時の制御信号により制御素子Q1がオンし、
td時〜の制御信号により制御素子Q2がオンす
る。
As shown in Fig. 2 a and b, when control signals with a predetermined pulse width are alternately input to both control terminals I1 and I2, the control element Q1 is turned on by the control signal from time ta to time ta'. After that, the control element Q2 is turned on by the control signal from time tb to time tb', and further, the control element Q1 is turned on by the control signal from time tc to time tc'.
Control element Q2 is turned on by the control signal from time td.

そこで第2図cに示すように、a点をb点との
間の電圧、すなわち出力電圧は、b点を基準電圧
点とした場合、ta時〜tb時に正電圧になり、tb時
〜tc時に負電圧になり、tc時〜td時に正電圧にな
り、出力電圧が正電圧と負電圧とに交互に変化す
る高周波電圧になる。
Therefore, as shown in Figure 2c, the voltage between point a and point b, that is, the output voltage, becomes a positive voltage from time ta to time tb, and from time tb to time tc, when point b is taken as the reference voltage point. At times, the voltage becomes negative, and from time tc to time td, it becomes a positive voltage, and the output voltage becomes a high-frequency voltage that alternately changes between positive and negative voltages.

一方、負荷Zが進み力率の場合、出力電圧の印
加により、a点とb点との間を流れる電流、すな
わち出力電流は、a点からb点の方向を正方向と
した場合、第2図dに示すように、負荷Zを流れ
る出力電流は、出力電圧の位相に対して進み位相
の高周波電流になる。
On the other hand, when the load Z has a leading power factor, the current flowing between points a and b due to the application of the output voltage, that is, the output current, is the second As shown in FIG. d, the output current flowing through the load Z becomes a high-frequency current with a leading phase with respect to the phase of the output voltage.

すなわち、たとえばta時の制御素子Q1のオン
により、同図eに示すように、ta時およびt〓時に
は、制御素子Q1に順方向電流が流れ、負荷Zに
は、電源E1、制御素子Q1、リアクトルLy、
負荷Z、電源E1の方向に出力電流が流れ、負荷
Zの共振により出力電流が零になるt〓時まで前述
の方向の出力電流が流れる。なお、t〓時、t〓時は
ta時〜ta′時の間の時刻である。
That is, for example, when the control element Q1 is turned on at the time of ta, a forward current flows through the control element Q1 at the time of ta and at the time of t, as shown in FIG. Reactor Ly,
The output current flows in the direction of the load Z and the power source E1, and the output current flows in the aforementioned direction until time t when the output current becomes zero due to the resonance of the load Z. In addition, t〓 time and t〓 time are
It is the time between ta time and ta′ time.

そしてt〓時に出力電流が零になると、出力電流
の方向が逆方向に反転し、第2図fに示すよう
に、ダイオードD1に順方向電流が流れ、負荷Z
には、負荷Z、リアクトルLy、ダイオードD1、
電源E1、負荷Zの方向の出力電流が流れる。
When the output current becomes zero at time t, the direction of the output current is reversed, and as shown in Figure 2 f, a forward current flows through the diode D1, and the load Z
includes load Z, reactor Ly, diode D1,
An output current flows in the direction of the power source E1 and the load Z.

さらに、ta′時には制御素子Q1への制御信号
が遮断されるとともに、tb時に制御素子Q2に制
御信号が入力されると、第2図fに示すように、
ダイオードD1に、電源E1、ダイオードD1、
制御素子Q2、電源E2の方向の逆回復電流が流
れるとともに、同図gに示すように、制御素子Q
2に順方向電流が流れ、負荷Zには、電源E2、
負荷Z、リアクトルLy、制御素子Q2、電源E
2の方向の出力電流が流れる。
Furthermore, when the control signal to the control element Q1 is cut off at the time ta' and the control signal is input to the control element Q2 at the time tb, as shown in FIG. 2f,
Diode D1, power supply E1, diode D1,
A reverse recovery current flows in the direction of the control element Q2 and the power source E2, and as shown in g of the figure, the control element Q
A forward current flows through load Z, and power source E2,
Load Z, reactor Ly, control element Q2, power supply E
Output current flows in two directions.

そしてダイオードD1の逆回復期間が終了する
と、制御素子Q2には出力電流のみが流れ、t〓時
に、負荷Zの共振により出力電流が零になると、
第2図hに示すように、ダイオードD2に順方向
電流が流れ、負荷Zには、負荷Z、電源E2、ダ
イオードD2、リアクトルLy、負荷Zの方向に
出力電流が流れる。
When the reverse recovery period of the diode D1 ends, only the output current flows through the control element Q2, and at time t, when the output current becomes zero due to the resonance of the load Z,
As shown in FIG. 2h, a forward current flows through the diode D2, and an output current flows through the load Z in the direction of the load Z, the power source E2, the diode D2, the reactor Ly, and the load Z.

さらに、hb′時に制御素子Q2への制御信号が
遮断されるとともに、tc時に制御素子Q1に制御
信号が入力されると、第2図hに示すように、ダ
イオードD2に電源E1、制御素子Q1、ダイオ
ードD2、電源E2の方向の逆回復電流が流れる
とともに、同図eに示すように、制御素子Q1に
順方向電流が流れ、負荷Zには、電源E1、制御
素子Q1、リアクトルLy負荷Z、電源E1の方
向の出力電流が流れる。
Further, when the control signal to the control element Q2 is cut off at the time hb' and the control signal is input to the control element Q1 at the time tc, the diode D2 is connected to the power source E1 and the control element Q1 , the diode D2, and the power source E2, and as shown in the figure e, a forward current flows in the control element Q1, and the load Z has the power source E1, the control element Q1, and the reactor Ly load Z. , an output current flows in the direction of the power source E1.

ところで両ダイオードD1,D2の逆回復電流
の流れる期間、すなわち逆回復期間は0.3〜1μsec
程度と長く、かつ、逆回復電流の大きさも非常に
大きいため、両制御素子Q1,Q2それぞれのオ
ン時に損失が増大し、両制御素子Q1,Q2を破
壊する恐れもある。
By the way, the period during which the reverse recovery current flows in both diodes D1 and D2, that is, the reverse recovery period, is 0.3 to 1 μsec.
Since the reverse recovery current is extremely long and the magnitude of the reverse recovery current is also very large, the loss increases when both control elements Q1 and Q2 are turned on, and there is a possibility that both control elements Q1 and Q2 may be destroyed.

そこで両ダイオードD1,D2の逆回復電流に
よる両制御素子Q1,Q2の破壊を防止するため
に、高速スイツチングのダイオードを両ダイオー
ドD1,D2とは別個に設けることが考えられる
が、この場合は、容量の大きなダイオードを設け
る必要があるとともに、構成が複雑化する欠点が
ある。
Therefore, in order to prevent destruction of both control elements Q1 and Q2 due to the reverse recovery current of both diodes D1 and D2, it is possible to provide a high-speed switching diode separately from both diodes D1 and D2, but in this case, This has the disadvantage that it is necessary to provide a diode with a large capacity and the configuration becomes complicated.

この発明は、前記の点に留意してなされたもの
であり、高周波インバータの制御素子に電界効果
トランジスタを用いて振動性負荷に高周波出力を
供給する高周波電源装置の制御方法において、前
記負荷を流れる前記高周波電源装置の出力電流お
よび前記負荷に印加される前記高周波電源装置の
出力電圧を検出するとともに、前記出力電流の検
出信号の位相を遅れ方向に移相して位相調整信号
を形成し、前記出力電圧の検出信号と前記位相調
整信号との位相比較にもとづき、前記出力電圧の
検出信号に対する前記位相調整信号の進み、遅れ
に応じて周波数が低,高変化する周波数パルスを
形成し、前記周波数パルスに比例して前記制御素
子の駆動周波数を可変することを特徴とする高周
波電源装置の制御方法を提供するものである。
The present invention has been made with the above-mentioned points in mind, and includes a control method for a high-frequency power supply device that uses a field-effect transistor as a control element of a high-frequency inverter to supply a high-frequency output to a vibrating load. detecting the output current of the high frequency power supply device and the output voltage of the high frequency power supply device applied to the load, and shifting the phase of the detection signal of the output current in a delay direction to form a phase adjustment signal; Based on the phase comparison between the output voltage detection signal and the phase adjustment signal, a frequency pulse whose frequency changes from low to high according to the lead or lag of the phase adjustment signal with respect to the output voltage detection signal is formed, and the frequency pulse is The present invention provides a method for controlling a high frequency power supply device, characterized in that the drive frequency of the control element is varied in proportion to the pulse.

したがつて、出力電流が出力電圧に対して常に
遅れ位相になり、第1図の高周波電源装置の振動
性負荷Zが常に遅れ力率の負荷に制御されたのと
等価になる。
Therefore, the output current always has a lagging phase with respect to the output voltage, and this is equivalent to the case where the oscillatory load Z of the high frequency power supply device shown in FIG. 1 is always controlled to a lagging power factor load.

そして、負荷Zが遅れ力率になると、第3図
a,bに示すように、t1時に制御素子I2への制
御信号の入力が遮断され、t2時〜t2′時に制御端
子I1に、t3時〜t3′時に制御端子I2に、t4時〜
t4′時に制御端子I1に、t5時に制御端I2に制
御信号が入力されることにより、出力電圧が同図
cに示すように、正電圧と負電圧との交互にパル
ス変化し、出力電流が同図dに示すように、出力
電圧に対して遅れ位相で変化する。
When the load Z has a lagging power factor, the input of the control signal to the control element I2 is cut off at time t1, and the input of the control signal to the control element I2 is interrupted at time t2 to t2', as shown in FIG. 3a and b. To the control terminal I2 at ~t3', to the control terminal I2 at t4~
By inputting a control signal to the control terminal I1 at time t4' and to the control terminal I2 at time t5, the output voltage changes pulses alternately between positive and negative voltages as shown in c in the figure, and the output current changes. As shown in d of the same figure, it changes with a lag phase with respect to the output voltage.

すなわち、たとえばt2時〜t2′時の制御信号に
より、第3図eに示すように、tx時には制御端子
Q1に順方向電流が流れ、負荷Zには、電源E
1、制御素子Q1、リアクトルLy、負荷Z、電
源E1の方向の出力電流が流れ、t2′時に制御素
子Q1への制御信号が遮断されると、負荷Zに
は、負荷Z、電源E2、ダイオードD2、リアク
トルLy、負荷Zの方向の出力電流が流れ、同図
fに示すように、ダイオードD2に順方向電流が
流れ、出力電流の向きは変化しない。
That is, for example, as shown in FIG. 3e, due to the control signal from time t2 to time t2', a forward current flows to the control terminal Q1 at time tx, and the load Z receives power from the power source E.
1. Output current flows in the direction of control element Q1, reactor Ly, load Z, and power source E1, and when the control signal to control element Q1 is cut off at time t2', load Z has load Z, power source E2, and diode. An output current flows in the direction of D2, the reactor Ly, and the load Z, and as shown in f in the figure, a forward current flows in the diode D2, and the direction of the output current does not change.

そしてt3時に制御素子Q2に制御信号が入力さ
れ、t3時より後のty時に出力電流が零になると、
第3図fに示すように、ダイオードD2に逆回復
電流が流れ、このとき、負荷Zには、電源E2、
負荷Z、リアクトルLy、ダイオードD2、電源
E2の方向の出力電流が流れる。
Then, at time t3, a control signal is input to control element Q2, and when the output current becomes zero at time ty, which is after time t3,
As shown in FIG. 3f, a reverse recovery current flows through the diode D2, and at this time, the load Z is connected to the power source E2,
Output current flows in the directions of load Z, reactor Ly, diode D2, and power source E2.

さらに、ダイオードD2の逆回復期間が経過す
ると、第3図gに示すように、制御素子Q2に順
方向電流が流れ、このとき、負荷Zには、電源E
2、負荷Z、リアクトルLy、制御素子Q2、電
源E2の方向の出力電流が流れる。
Furthermore, when the reverse recovery period of the diode D2 has elapsed, a forward current flows through the control element Q2 as shown in FIG.
2. Output current flows in the directions of load Z, reactor Ly, control element Q2, and power source E2.

そしてt3′時に制御素子Q2への制御信号が遮
断されると、第3図gに示すように、制御素子Q
2の順方向電流が遮断されるが、同図hに示すよ
うに、ダイオードD1に順方向電流が流れ、この
とき、負荷Zには、負荷Z、リアクトルLy、ダ
イオードD1、電源E1、負荷Zの方向の出力電
流が流れる。
When the control signal to the control element Q2 is cut off at time t3', the control signal to the control element Q2 is interrupted as shown in FIG. 3g.
However, as shown in h of the figure, a forward current flows through the diode D1, and at this time, the load Z includes the load Z, the reactor Ly, the diode D1, the power source E1, and the load Z. The output current flows in the direction of .

さらに、t4時に制御素子Q1に制御信号が入力
され、t4時より後のtz時に出力電流が零になる
と、第3図hに示すように、ダイオードD1に逆
回復電流が流れ、負荷Zには、負荷Z、電源E
1、ダイオードD1、リアクトルLy、負荷Zの
方向の出力電流が流れる。
Furthermore, when a control signal is input to the control element Q1 at time t4 and the output current becomes zero at time tz, which is after time t4, a reverse recovery current flows through the diode D1 as shown in Fig. 3h, and the load Z , load Z, power supply E
1. Output current flows in the direction of diode D1, reactor Ly, and load Z.

そしてダイオードD1の逆回復期間が経過する
と、第3図eに示すように、制御素子Q1に順方
向電流が流れ、以降同様の動作をくり返す。
When the reverse recovery period of the diode D1 has elapsed, a forward current flows through the control element Q1, as shown in FIG. 3e, and the same operation is repeated thereafter.

したがつて両ダイオードD1,D2の逆回復電
流は両制御素子Q1,Q2を流れることがなく、
逆回復電流による両制御素子Q1,Q2の破壊な
どを防止することができるものである。
Therefore, the reverse recovery current of both diodes D1 and D2 does not flow through both control elements Q1 and Q2,
This makes it possible to prevent destruction of both control elements Q1 and Q2 due to reverse recovery current.

つぎに、この発明の高周波電源装置の制御方法
を、その実施例を示した第4図以下の図面ととも
に説明する。
Next, a method for controlling a high frequency power supply device according to the present invention will be explained with reference to the drawings from FIG. 4 showing an embodiment thereof.

まず、1実施例を第4図ないし第6図とともに
説明する。
First, one embodiment will be described with reference to FIGS. 4 to 6.

第4図において第1図と同一記号は同一のもの
を示し、Tpは振動性負荷Zに印加される出力電
圧検出用の電圧検出器であり、変成器などからな
るとともに、第5図aに示すように、負荷Zを接
続したときの出力電圧の変化に従つて変化する電
圧検出信号Saを出力する。Tcは負荷Zとa点と
の間に設けられた電流検出器であり、変流器など
からなるとともに、第5図bに示すように、負荷
Zを流れる出力電流に従つて変化する電流検出信
号Sbを出力する。
In Fig. 4, the same symbols as in Fig. 1 indicate the same things, and Tp is a voltage detector for detecting the output voltage applied to the vibratory load Z. As shown, a voltage detection signal Sa that changes according to the change in output voltage when a load Z is connected is output. Tc is a current detector installed between the load Z and point a, and consists of a current transformer, etc., and as shown in Figure 5b, the current detector changes according to the output current flowing through the load Z. Outputs signal Sb.

そして電流検出信号Sbが位相調整器Prに入力
され、第5図cに示すように、電流検出信号Sb
の位相を90゜遅らせた位相調整信号Scが、位相調
整器Prから出力される。なお、位相調整器Prは
抵抗、コンデンサなどからなり、入力信号の位相
を調整することができる。
Then, the current detection signal Sb is input to the phase adjuster Pr, and as shown in FIG. 5c, the current detection signal Sb
A phase adjustment signal Sc whose phase is delayed by 90° is output from the phase adjuster Pr. Note that the phase adjuster Pr consists of a resistor, a capacitor, etc., and can adjust the phase of the input signal.

さらに、電圧検出信号Saが電圧用波形整形器
Wvに入力され、第5図bに示すように、電圧検
出信号の正の半波を矩形波に整形した電圧検出パ
ルスSbが波形整形器Wvから出力されるとともに
位相調整信号Scが電流用波形整形器Wiに入力さ
れ、同図eに示すように、位相調整信号Scの正
の半波を矩形波に整形した電流検出パルスSeが
波形整形器Wiから出力される。
Furthermore, the voltage detection signal Sa is connected to the voltage waveform shaper.
Wv, and as shown in Figure 5b, the voltage detection pulse Sb, which is the positive half wave of the voltage detection signal shaped into a rectangular wave, is output from the waveform shaper Wv, and the phase adjustment signal Sc is converted into a current waveform. The current detection pulse Se is inputted to the shaper Wi, and is outputted from the waveform shaper Wi by shaping the positive half wave of the phase adjustment signal Sc into a rectangular wave as shown in FIG.

そして両検出パルスSd,Seが排他的論理和ゲ
ートなどからなる比較器Gに入力されて位相比較
され、第5図fに示すように、両検出パルスSd,
Seが、論理1(以下“1”と称する)、論理0(以
下“0”と称する)、または“0”,“1”の組み
合わせで入力されたときにのみ“1”になる比較
パルスSfが、比較器GからローパスフイルタLf
に出力され、同図gに示すように、比較パルスSf
を平滑した平滑信号Sgが、ローパスフイルタLf
から電圧/周波数変換器(V/F)に出力され
る。
Then, both detection pulses Sd and Se are inputted to a comparator G consisting of an exclusive OR gate and the phases are compared, and as shown in FIG. 5f, both detection pulses Sd,
Comparison pulse Sf that becomes "1" only when Se is input as logic 1 (hereinafter referred to as "1"), logic 0 (hereinafter referred to as "0"), or a combination of "0" and "1" However, from the comparator G to the low pass filter Lf
As shown in g in the figure, the comparison pulse Sf
The smoothed signal Sg is passed through the low-pass filter Lf
is output to a voltage/frequency converter (V/F).

なお、変換器(V/F)は電圧制御発振器など
からなり、第6図に示すように、入力電圧に比例
して出力周波数が変化する。
The converter (V/F) is composed of a voltage controlled oscillator or the like, and as shown in FIG. 6, the output frequency changes in proportion to the input voltage.

さらに、変換器(V/F)からパルス増幅器
Paに、平滑信号Sgの電圧に比例して周波数の変
化する周波数パルスShが出力され、パルス増幅
器Paから両制御端子I1,I2それぞれに周波
数パルスShの周波数に比例した第3図a,bの
制御信号が出力され、両制御素子Q1,Q2のオ
ン,オフ,すなわち駆動周波数が制御される。な
お、Aは制御部である。
Furthermore, from the converter (V/F) to the pulse amplifier
A frequency pulse Sh whose frequency changes in proportion to the voltage of the smoothed signal Sg is outputted to Pa, and a frequency pulse Sh whose frequency changes in proportion to the voltage of the smoothed signal Sg is outputted from the pulse amplifier Pa to both control terminals I1 and I2 respectively. A control signal is output, and the on/off, ie, drive frequency, of both control elements Q1 and Q2 is controlled. Note that A is a control section.

そして出力電流の位相が出力電圧の位相より進
み始めると、第5図eの電流検出パルスSeの位
相が進み、該検出パルスSeの立ち上がりタイミ
ングが、同図dの電圧検出パルスSdの立ち上が
りタイミングに近づき、同図fに示す比較パルス
Sfの“1”の幅が狭くなり、“0”の幅が長くな
り、同図gに示す平滑信号Sgが低くなり、変換
器(V/F)から出力される周波数パルスShの
周波数が低くなり、パルス増幅器Paから出力さ
れる制御信号により、出力電流の位相が遅れる方
向に制御され、出力電流の位相が出力電圧の位相
より所定量だけ遅れるように調整制御される。
When the phase of the output current starts to advance from the phase of the output voltage, the phase of the current detection pulse Se shown in FIG. 5e advances, and the rising timing of the detection pulse Se coincides with the rising timing of the voltage detection pulse Sd shown in As the comparison pulse approaches, the comparison pulse shown in f of the same figure
The width of "1" of Sf becomes narrower, the width of "0" becomes longer, the smoothed signal Sg shown in g in the figure becomes lower, and the frequency of the frequency pulse Sh output from the converter (V/F) becomes lower. The control signal output from the pulse amplifier Pa controls the phase of the output current so that it lags, and adjusts and controls the phase of the output current so that it lags the phase of the output voltage by a predetermined amount.

逆に、出力電流の位相が出力電圧の位相より遅
れすぎると、電流検出パルスSeの立ち上がりタ
イミングが、第5図eのタイミングよりさらに遅
れ、このとき、比較パルスSfの“1”の幅が広く
なり、変換器(V/F)から出力される周波数パ
ルスShの周波数が高くなり、出力電流の位相が
進む方向に制御され、出力電流の位相が出力電圧
の位相より所定量だけ遅れるように調整制御され
る。
Conversely, if the phase of the output current lags the phase of the output voltage too much, the rising timing of the current detection pulse Se will be further delayed from the timing shown in Figure 5e, and at this time, the width of "1" of the comparison pulse Sf will become wider. The frequency of the frequency pulse Sh output from the converter (V/F) increases, the phase of the output current is controlled in the direction of advancing, and the phase of the output current is adjusted so that it lags the phase of the output voltage by a predetermined amount. controlled.

したがつて常に、出力電流の位相が出力電圧の
位相より所定量だけ遅れることになり、第3図の
場合と同様に、両ダイオードD1,D2の逆回復
電流は、両制御素子Q1,Q2を流れることがな
く、逆回復電流による両制御素子Q1,Q2の破
壊などを防止することができる。
Therefore, the phase of the output current always lags the phase of the output voltage by a predetermined amount, and as in the case of FIG. Since no current flows, destruction of both control elements Q1 and Q2 due to reverse recovery current can be prevented.

つぎに、他の実施例を第7図とともに説明す
る。
Next, another embodiment will be described with reference to FIG.

第7図において、第4図と同一記号は同一のも
のを示し、異なる点は、リアクトルLyとa点と
の間に、インバータからみた負荷Zの力率が1に
なるような共振用コンデンサCyを設けた点であ
る。
In Fig. 7, the same symbols as in Fig. 4 indicate the same things, and the difference is that a resonant capacitor Cy is installed between the reactor Ly and point a so that the power factor of the load Z as seen from the inverter is 1. The point is that

そしてリアクトルLyとコンデンサCyの共振周
波数fa=1/(2π√)が、負荷Zの共振周
波数fb=1/(2π√)より若干低くなり、
インバータから見た力率は遅れ力率になり、逆回
復電流による両制御素子Q1,Q2の破壊が防止
されるとともに、インバータの出力周波数が負荷
Zの共振周波数fbに一致し、インバータの効率を
高めることができる。
Then, the resonant frequency fa = 1/(2π√) of the reactor Ly and capacitor Cy becomes slightly lower than the resonant frequency fb = 1/(2π√) of the load Z,
The power factor seen from the inverter becomes a lagging power factor, which prevents destruction of both control elements Q1 and Q2 due to reverse recovery current, and makes the output frequency of the inverter match the resonant frequency fb of the load Z, increasing the efficiency of the inverter. can be increased.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の高周波電源装置に適用される高
周波インバータの結線図、第2図a〜hは第1図
の動作説明用タイミングチヤート、第3図以下の
図面はこの発明の高周波電源装置の制御方法を示
し、第3図a〜hは原理説明用タイミングチヤー
ト、第4図は1実施例の結線図、第5図a〜gは
第4図の動作説明用タイミングチヤート、第6図
は第4図の電圧/周波数変換器の入力電圧に対す
る出力周波数の特性図、第7図は他の実施例の結
線図である。 A……制御部、Q1,Q2……制御素子、Z…
…振動性負荷、Tp……電圧検出器、Tc……電流
検出器、Pr……位相調整器、Wv,Wi……波形整
形器、G……比較器、Lf……ローパスフイルタ、
(V/F)……電圧/周波数変換器、Pa……パル
ス増幅器。
Fig. 1 is a wiring diagram of a high-frequency inverter applied to a conventional high-frequency power supply, Fig. 2 a to h are timing charts for explaining the operation of Fig. 1, and Fig. 3 and the following drawings are a diagram of a high-frequency inverter according to the present invention. 3A to 3H are timing charts for explaining the principle, FIG. 4 is a wiring diagram of one embodiment, FIGS. 5A to 5G are timing charts for explaining the operation of FIG. 4, and FIG. FIG. 4 is a characteristic diagram of the output frequency with respect to the input voltage of the voltage/frequency converter, and FIG. 7 is a connection diagram of another embodiment. A...Control unit, Q1, Q2...Control element, Z...
...Vibrating load, Tp...Voltage detector, Tc...Current detector, Pr...Phase adjuster, Wv, Wi...Waveform shaper, G...Comparator, Lf...Low pass filter,
(V/F)...Voltage/frequency converter, Pa...Pulse amplifier.

Claims (1)

【特許請求の範囲】 1 高周波インバータの制御素子に電界効果トラ
ンジスタを用いて振動性負荷に高周波出力を供給
する高周波電源装置の制御方法において、 前記負荷を流れる前記高周波電源装置の出力電
流および前記負荷に印加される前記高周波電源装
置の出力電圧を検出するとともに、前記出力電流
の検出信号の位相を遅れ方向に移相して位相調整
信号を形成し、前記出力電圧の検出信号と前記位
相調整信号との位相比較にもとづき、前記出力電
圧の検出信号に対する前記位相調整信号の進み、
遅れに応じて周波数が低、高変化する周波数パル
スを形成し、前記周波数パルスに比例して前記制
御素子の駆動周波数を可変することを特徴とする
高周波電源装置の制御方法。
[Scope of Claims] 1. A method for controlling a high-frequency power supply device that supplies a high-frequency output to a vibrating load using a field-effect transistor as a control element of a high-frequency inverter, comprising: an output current of the high-frequency power supply device flowing through the load and the load; detects the output voltage of the high frequency power supply applied to the output voltage, and shifts the phase of the output current detection signal in the delay direction to form a phase adjustment signal, and outputs the output voltage detection signal and the phase adjustment signal. an advance of the phase adjustment signal with respect to the detection signal of the output voltage based on a phase comparison with the output voltage;
A method for controlling a high frequency power supply device, comprising: forming a frequency pulse whose frequency changes from low to high according to a delay, and varying the driving frequency of the control element in proportion to the frequency pulse.
JP57197369A 1982-11-08 1982-11-08 Controlling method for high frequency power source Granted JPS5986481A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57197369A JPS5986481A (en) 1982-11-08 1982-11-08 Controlling method for high frequency power source

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57197369A JPS5986481A (en) 1982-11-08 1982-11-08 Controlling method for high frequency power source

Publications (2)

Publication Number Publication Date
JPS5986481A JPS5986481A (en) 1984-05-18
JPH0245438B2 true JPH0245438B2 (en) 1990-10-09

Family

ID=16373345

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57197369A Granted JPS5986481A (en) 1982-11-08 1982-11-08 Controlling method for high frequency power source

Country Status (1)

Country Link
JP (1) JPS5986481A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6181182A (en) * 1984-09-27 1986-04-24 High Frequency Heattreat Co Ltd Parallel inverter

Also Published As

Publication number Publication date
JPS5986481A (en) 1984-05-18

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