JPH0245828A - Method and device for comparing data - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data comparison device in an information processing device, and particularly to a data comparison method suitable for comparison processing between comparison data on a bus and reference data. Regarding equipment.

[Conventional technology]

A conventional technique is shown in FIG. For example, in the data comparison device 25 that periodically compares the comparison data on the bus 36 with reference data in units of units.

When starting up a system including the data comparison device 25,
Alternatively, during normal operation, a predetermined signal output from the information processing section 31 of a host or the like is decoded by the writing circuit 27, and a write signal causes the plurality of groups of reference data to be output from the information processing section 31. Each unit amount of data within a group is sequentially written into a predetermined memory area of the reference data setting section 26 via the bus 33, data switching section 28, and bidirectional data bus 34. In the system state opposite to the above, that is, during normal operation or at system start-up, the data bus 33 of the information processing section 31 is opened in the data switching section 28, and the bidirectional data bus 34 is
It is switched to the internal data bus 35 of the data comparison device 25. As a result, the data comparison device 25 becomes irrelevant to the in-system processing of the information processing section 31. During this period, the counter A3 is incremented when the comparison data is determined.
The count value of 7, the count value of the counter B38 that is incremented at the timing when the reference data is read during the comparison data determination period, and the comparison data judgment mode initially set by the system are decoded in the readout circuit 29 and read out. Output as a signal. The reference data is arbitrarily read out from a predetermined memory area of the reference data setting section 26 by the read signal,
It is output to the comparison circuit 30 and compared with the comparison data.

If the comparison result is a mismatch, a mismatch signal is input from the comparison circuit 30 to the readout circuit 29, and a readout signal for selecting other reference data is generated. In response to the read signal, reference data different from the above is read from a predetermined memory area of the reference data setting section 26, the counter B3g is incremented, and the six reference data to be compared with the comparison data are read out. There is a possibility that the comparison data is repeated multiple times in succession during the determination period of the comparison data. Note that the comparison permission signal inputted from the write circuit 27 to the comparison circuit 30 becomes active after the reference data of the plurality of groups are written from the information processing section 31 to the reference data setting section 26. When the comparison permission signal is active, the comparison result between the comparison data and the reference data becomes valid. If the comparison results match, the comparison data is taken into the buffer 32.

Here, the memory area of the reference data setting section 26 is composed of memory cells that have a common data exit and can be accessed separately for writing and reading, for example, random access memory cells, and is composed of n groups ( n: a positive integer) reference data are set, and one group of the reference data is composed of m units (m: a positive integer) of unit quantity, for example, 16 bits.

Incidentally, related devices of this type include, for example, Japanese Patent Application Laid-Open No. 61-278238.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, for example, if the reference data settings are changed while the system is online, writing must be performed after returning to the online state. In this case, if the comparison data on the bus is, for example, transmission data on a transmission medium in a communication system, the transmission data may be missed by placing the system in an offline state. Also, during the transmission data confirmation period,
Since various reference data are read and compared multiple times, it is difficult to speed up the comparison process.

An object of the present invention is to provide a means for arbitrarily writing reference data in a predetermined memory area even when the system is online.

Another object of the present invention is to provide means for efficiently reading out optimal reference data.

Another object of the present invention is to provide a means for efficient comparison processing by simplifying control of comparison and determination between comparison data and reference data.

[Means to solve the problem]

As shown in FIG. 1, the present invention provides a circuit that has a memory area for storing multiple groups of reference data, separate data entry and exit, and can be accessed for writing and reading data independently. a memory cell having a
For example, it is realized by a 2-port random access memory cell. Further, in the present invention, as shown in FIG. 2, information included in the comparison data is held as a flag, and the reference data is read from the predetermined memory area using the flag.

Further, in the present invention, as shown in FIG. 3, a flag holding a comparison result between intermediate comparison data and reference data;
Using the flag that holds the comparison result between the final comparison data and reference data, the flag that holds the information of the comparison data, and the comparison data judgment mode that is initially set by the system, the final During the comparison data determination period, continuous comparison data forming the unit group is determined.

[Effect]

The memory area that stores multiple groups of reference data has separate buses for data input and output, and can be accessed separately for writing and reading. It is possible to write reference data. In other words, even if the transmission data on the transmission medium is being compared with the reference data read from the memory area, it is possible to write the arbitration data using a predetermined write signal, so there is no possibility that the transmission data will be missed. does not occur.

In addition, since reading of the reference data from the memory area is possible using a flag that holds information of the transmission data and a count value of a counter that is incremented when the transmission data is determined, the optimal reference data can be read from the memory area. can be read from a predetermined memory area.

In addition, in the comparison circuit that compares the transmitted data with the reference data, there is a flag that holds the comparison result between the intermediate transmission data and the reference data, and a flag that holds the comparison result between the final comparison data and the reference data. , a flag holding information of the transmission data, and a comparison data judgment mode,
By making the determination at the same time during the final comparison data determination period of the unit group, comparison determination control is simplified.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. The information processing device includes an information processing section 16, a data comparison device 11, and a buffer 17. The data comparison device 11 is
It is composed of a reference data setting section 12, a write circuit 13, a read circuit 14, a comparison circuit 15, a counter 21, and a flag 22.

The reference data setting unit 12 is a memory cell having a circuit that has separate input and output ports for data and can be accessed for writing and reading data independently, for example, a two-port random access memory cell having a plurality of words. It is composed of memory cells or flip-flop cells.

In the data comparison device 11 that synchronously compares the comparison data on the bus 20 with 16 bits of reference data every unit amount, for example, every 16 bits, the reference data is transferred from the information processing unit 16 to a dedicated data bus. The write circuit 1 receives a write instruction from the information processing section 16 via the information processing section 18.
The data is written into a predetermined memory area of the reference data setting section 12 by the write signal outputted from step 3. Also, from a predetermined memory area of the reference data setting section 12.

via a proprietary data bus 19 to the comparison circuit 15.

A counter 21 that is incremented when the comparison data is determined.
The reference data is read out by the readout signal decoded by the value of the flag 22 that holds the information of the comparison data, and is output to the comparison circuit 15 and compared with the comparison data. be done. The comparison result is
Based on the value of the flag 22 and the comparison data determination mode, the comparison data on the bus 20 is taken into the buffer 17.

The write signals Wl, W which are the outputs of the write circuit 13
2. . . . wn (n: positive integer), and read signals rl and rZ which are outputs of the read circuit 14.

. . rn (n: positive integer) represents the reference data 1 . Standard data 2. ... Corresponding to reference data n (n: a positive integer), when there is a write instruction from the information processing section 16, the write signal wt (which is the output of the write circuit 13) is
i: an integer satisfying 1≦i≦n) becomes active, and reference data i is set.

Similarly, when the read signal rj (j: an integer of l≦j≦n), which is the output of the read circuit 14, is active, the reference data j is read out and output to the comparison circuit 15.

The write circuit 13 and the read circuit 14 are independent from each other and do not interfere with each other.

As described above, according to this embodiment, a flag is added compared to the conventional technology, but a data switching unit and a counter are not required, and a comparison permission signal is also not required, so the configuration of the data comparison device is simplified. can contribute to miniaturization. Furthermore, for operational reasons, it becomes possible to write dynamic reference data.

Can accommodate functional expansion. Furthermore, it becomes possible to read out optimal reference data, and it becomes easy to control the determination of continuous comparison data.

It should be noted that the present invention can also be applied to serial data after serial/parallel data conversion, and similar effects can be achieved.

FIG. 5 shows how to use it in a communication system.

A method for comparing a destination address field of a received frame, a method for comparing a source address field of a received frame, and a routing information field of a received frame for comparing a received frame on a transmission medium, which is comparison data on a bus, with self-address data, which is reference data. A similar effect can also be achieved using a comparison method.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to dynamically rewrite reference data in a data comparison method for an information processing device, etc., and this has the effect of increasing the efficiency of information transmission. Further, according to one aspect of the present invention, it becomes possible to read out the optimum reference data, and it becomes easy to control the comparison and judgment of continuous comparison data, so that there is an effect of increasing the efficiency of comparison processing.

[Brief explanation of the drawing]

1 to 6 are diagrams showing an embodiment of the present invention, and FIG. 7 is a diagram showing a conventional embodiment. 1...Memory area, 2,22...Flag, 3,4,
6゜14.29...readout circuit, 5,9,15.3
0...Comparison circuit, 11.25...Data comparison device,
12゜26...Reference data setting section. Figure 1 Figure 4

Claims (1)

[Claims] 1. A memory area for storing a plurality of groups of reference data for determining comparison data on a bus by data comparison, and writing the reference data in a predetermined memory area and writing the written reference data. Read data from the predetermined memory area,
In a data comparison in which the comparison data is compared with the reference data, the memory cell has a circuit in which the memory area has separate data entry and exit, and can be accessed for data writing and reading independently. A data comparison device comprising a plurality of devices. 2. Data comparison: has a memory area for storing multiple groups of reference data for determining comparison data on the bus, writes the reference data in a predetermined memory area, and writes the written reference data to the predetermined memory. Read from the area,
In data comparison in which the comparison data is compared with the reference data, the memory area is a memory cell capable of simultaneous data write and read access operations, and data input/output processing in separate systems. A data comparison device comprising a plurality of devices. 3. Information possessed by comparison data on the bus is held as a flag, and reference data is read from a predetermined memory area based on the held flag and the count value of a counter that is incremented when the comparison data is determined. The data comparison method according to paragraph 1. 4. The comparison data on the bus is an element constituting a unit group, and the comparison results between the comparison data and the reference data are sequentially held as flags at the same timing as when the comparison data is determined, The retained flag, and
A flag that holds the comparison result between the final comparison data and reference data in the unit group, a flag that holds the information of the comparison data, and a comparison data judgment mode that is initially set by the system, 2. The data comparison device according to claim 1, further comprising a comparison circuit for determining unit groups. 5. A reference data setting section including a memory area for storing a plurality of groups of reference data for determining comparison data on the bus in the data comparison system, and writing of the reference data into a predetermined memory area in the reference data setting section. It consists of a write circuit for instructing, a read circuit for instructing reading of the reference data from a predetermined memory area in the reference data setting section, and a comparison circuit for comparing the comparison data with the reference data. The reference data setting section includes the memory area made up of a plurality of memory cells each having a circuit that can independently write and read data; A data comparison device characterized in that it controls writing to the reference data setting section and reading from the reference data setting section. 6. The configuration of the memory area for data comparison, where the memory cell has a circuit that has separate data inlets and outlets and can be accessed for data writing and reading independently, as a 2-port random access memory. A configuration of a memory area in data comparison characterized by cells. 7. In the structure of the memory area for data comparison, a memory cell having a circuit that has separate data entry and exit and can be accessed for data writing and reading independently is a flip-flop cell. A configuration of a memory area in data comparison characterized by. 8. Comparison of received frames on a transmission medium in a station connected to a transmission medium of a communication system, the self-address data including a memory area for storing self-address data for determining a destination address field in the received frame. a setting section; a write circuit for instructing writing of the self-address data into a predetermined memory area in the self-address data setting section; and a writing circuit for instructing reading of the self-address data from the predetermined memory area in the self-address data setting section. and a comparison circuit that compares the destination address field in the received frame with the self-address data, and the memory area of the self-address data setting section has separate data entry and exit. 1. A destination address field comparison device for a received frame in a communication system, comprising memory cells each having a circuit that can be independently accessed for writing and reading data. 9. A source address field comparison method, characterized in that it is used in the comparison device according to claim 8. 10. A method for comparing routing information fields of received frames in a communication system, characterized in that it is used in the comparison device according to claim 8.