JPH0245828Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a target detection device for an aircraft or the like in radar signal processing. The target detection device calculates a value obtained by summing the data N clocks ago using an adder and averaging the contents of the shift register, which is set as a midpoint, and a value obtained by summing the data N clocks later using an adder and averaging the contents. This device performs target detection by comparing the values, outputting the larger value, and using the content of the shift register and the comparison circuit to take the one midpoint.

This invention is a target detection device in which one adder can be omitted instead of the two adders used in the conventional target detection device.

[Prior art]

Here, a conventionally used target detection device will be described for comparison. FIG. 1 is an example of a block diagram of a conventionally used target detection device. In FIG. 1, input data _D1 is input to shift registers 1a to 1c every clock. The input data are summed and averaged by adders, respectively, and input to the comparator circuit 4. The output of the comparison circuit 4 is input to the selector 3, which compares the average data from the shift register 1b taken 16 clocks ago with the average data 16 clocks later, and outputs the larger value _D2 . After that 1
The comparison circuit 5 compares the value _D3 to be the current midpoint of the clock with the larger value _D2 , and determines the value to be the current midpoint of one clock that is higher than the larger value _D2 .
If D ₃ is larger, it outputs "1" and considers it to be the target.

[Summary of the idea]

This invention is characterized in that by changing the use of the shift register, one of the two adders conventionally used in the target detection device can be omitted.

[Example of idea]

FIG. 2 is a block diagram showing the target detection device of this invention.

In the figure, 6a is the first shift register;
b is a second shift register, 6c is a third shift register, 7 is an adder, 8 is a first comparison circuit, 9
1 is a selector, and 10 is a second comparison circuit. The input signal D5 is input to the first and second shift registers 6a and 6b every clock. The input data is summed and averaged by the adder 7 to produce an output signal.
_D6 , one of which is sent to the first comparison circuit 8 and selector 9, and the other is sent to the third shift register 6c.
are input respectively. Here, the third shift register 6c takes timing so that the average value 16 clocks later, which is symmetrical to the average value of the data sum 16 clocks ago, is output from the second shift register 6b, which is set as a certain midpoint. Therefore, the number of shift registers has been adjusted. Thereafter, the average data 16 clocks ago and the average data 16 clocks later from the second shift register 6b, which is the midpoint, are compared by the first comparison circuit 8, and the larger value _D7 is output. In the second comparison circuit 10, if the value _D8 , which is the current midpoint of one clock, is larger than the output data _D7 of the selector, it outputs "1" and regards it as a target object.

By partially changing the use of the shift register in the target detection device as described above, it is possible to omit one adder.

This idea is GO-CFAR (Greatest of
Constant Falce Alarm Rate), but it is not limited to this.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventionally used target detection device, and FIG. 2 is a diagram showing a target detection device according to this invention. In the figure, 1 is a shift register, 2 is an adder, 3 is a selector, 4 is a comparison circuit, 5 is a comparison circuit, 6a,
6b and 6c are first, second, and third shift registers, 7 is an adder, 8 is a first comparison circuit, 9 is a selector, and 10 is a second comparison circuit.

Claims (1)

[Scope of utility model registration request] a first shift register that stores the video received by the radar every clock; an adder that sums and averages the contents of the shift register every clock; and a shift register that shifts the output of the first shift register; a second shift register for outputting content indicating the midpoint; and a third shift register for shifting the output of the adder.
a first comparison circuit and selector that selects the larger of the outputs of the adder and the third shift register, and compares the output of the selector with the output of the second shift register. A target detection device comprising a second comparison circuit.