JPH0245843A - Register and memory switching circuit - Google Patents

Abstract

PURPOSE:To simplify address control by selectively switching an access to a register group, to which an address is defined, to one part of a memory address space based on a reading and writing control signal to the specified memory address of a memory to be inputted. CONSTITUTION:When address designating inputs Ao-An are inputted from an external part to a register selecting circuit 1 and a memory selecting circuit 2, it is decided whether a final address is inputted or not. When the input is detected to be the final address and a reading signal RD is an 'H' level simultaneously, the output of an AND 1 goes to be the 'H' level and an FF 13 is set. Then, an FF 14 is reset and an address to a register array 24 is allocated to one part of the memory address space. Next, when a chip select signal CS goes to be the 'H' level, a register selecting signal SEL 1 is sent from an AND 3 to the register array 24.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a circuit in which a group of registers and memory whose functions are defined in advance are mixed and allocated in a predetermined address space, and in particular, The present invention relates to a register/memory switching circuit that switches access between a group of registers and a memory.

[Conventional technology]

FIG. 4 is a configuration block diagram showing an example of a conventional register/memory switching circuit, in which 21 is a memory address decoder, and address designation manual A is used. ~An is decoded to specify the address of the memory cell array 23. 22 is a register address decoder, and address designation manual A is provided. -An is decoded to specify the address of the register array 24. 25 is a functional logic that executes a predetermined functional process according to the contents written to each register of the register array 24, for example, the memory cell array 23. It controls the input/output data buffer 26 and controls data writing/data reading from the data input/output terminals D0 to Dm based on the read signal RD, write signal WR, and element selection signal CS.

FIG. 5 is a schematic diagram illustrating the memory map of the register array 24 and memory cell array 23 shown in FIG. This corresponds to the case where the area is allocated to a predetermined address space and the shaded area is an undefined area.

FIG. 2B shows a second memory map state, which corresponds to a state in which the register array 24 and the memory cell array 23 are allocated to a predetermined address space, with no free space left in the predetermined address space.

Next, the operation will be explained.

The addresses AO to An specified from the outside are processed by the memory address decoder 21. It is decoded by the register address decoder 22, one word of the memory cell array 23 or the register array 24 is specified corresponding to each decoding result, and data is input/output to one word of memory or register via the input/output data buffer 26. Functional logic 25 controls writing/reading of data from terminals D0 to Dm based on read signal RD, write signal WR, and element selection signal (chip select signal) C3.

[Problem to be solved by the invention]

However, since the conventional register/memory switching circuit is configured as described above, an empty area may occur in the memory space as shown in FIG. Since the entire memory space cannot be defined as a memory cell array area, the external circuit becomes complicated and
There was a serious problem in that the control program's access address management became complicated.

This invention was made to solve the above problems, and it is possible to expand the memory space by defining a memory cell area throughout a predetermined address space and switching the address space as an area for a register group as appropriate. It is an object of the present invention to provide a register/memory switching circuit that can efficiently switch register/memory access in accordance with the program execution state.

[Means to solve the problem]

The register/memory switching circuit according to the present invention provides access to a register group whose address is defined in a part of the memory address space based on an input read/write control signal for a specific memory address of the memory, or a specific register address of the register group. A switching means is provided for selectively switching access to the memory defined in the entire memory address space based on a read/write control signal for the memory address space.

[Effect]

In this invention, when a read/write control signal for a specific memory address of the memory or a read/write control signal for a specific register address of a register group is input, the switching means switches the register or group whose address is defined in a part of the memory address space. or accesses to memories defined in the entire memory address space can be selectively switched to enable addressing of memories and register groups in the same memory space.

(Embodiment) FIG. 1 is a block diagram illustrating the configuration of a register/memory switching circuit showing an embodiment of the present invention. Reference numeral 1 indicates a register selection circuit, and numeral 1 designates a register selection circuit, in which external address designation manual input A0 to A
n is decoded to decode a specific memory address, register array 24 is set to a selected state, and memory cell array 23 is set to a non-selected state. Reference numeral 2 denotes a memory selection circuit which decodes external address designation signals A and -An to decode a specific memory address (for example, the final address), puts the memory cell array 23 in a selected state, and makes the register array 24 in a non-selected state. do.

Note that the register selection circuit 1 and the memory selection circuit 2 constitute the switching means of the present invention, and control signals for reading and writing to a specific memory address of the memory (memory cell array 23) or reading and writing control to a specific register address of the register array 24 that is a register group. When a signal is input manually, access to a register group whose address is defined in a portion of the memory address space (see the address map shown in FIG. 2(a)) or access to the entire memory address space (see the address map shown in FIG.
Access to the memory defined in the memory map shown in FIG. 3(b) is selectively switched to enable addressing of memories and register groups in the same memory space.

FIG. 3 is a circuit block diagram illustrating the configuration of the register selection circuit 1 or memory selection circuit 2 shown in FIG. When it is decoded by ~An that a specific memory address, for example, the final address, has been designated and input, an enable signal is output to one end of the AND gate AND1. A read signal RD, which is a read/write control signal, is input to the other end of the AND gate AND1, and when the AND of both is established, the flip-flop (
FF) 13 and outputs a control signal to reset FF 14.

Reference numeral 12 denotes a specific register address decoding circuit, which outputs an enable signal to one end of an AND gate AND2 when it decodes that a specific register address has been designated by an external address designation input A, xAn. A read signal RD, which is a read/write control signal, is input to the other end of the AND gate AND2, and when the AND of the two is established, it outputs a control signal that resets the flip-flop (FF) 13 in the subsequent stage and sets the FF 14. .

AND3 is an AND gate, which is a register selection signal 5EL1 that selects access to the register array 24 when both the output of FF13 and the chip select signal C5 are at H level.
is output to the register array 24.

AND4 is an AND gate, and a memory selection signal 5EL2 that selects access to the memory cell array 23 when both the output of the FF 14 and the chip select signal C3 are at H level.
is output to the memory cell array 23.

As described above, when the register selection signal 5EL1 is output, the memory cell array 23 is in a non-selected state, and when the memory selection signal 5EL2 is output, the register array 24 is in a non-selected state.

Next, the operation will be explained.

The address and designation input AoNAn from the outside is the register selection circuit 1. When input to the memory selection circuit 2, it is determined whether or not a specific address has been input. For example, if it is decoded that the final address of the memory address space defined in the memory cell array 23 has been specified, that is, as shown in FIG. If the specific memory address decoding circuit 11 determines that the final address has been designated and the read signal RD is at H level at that time, the output of the AND gate ANDI becomes H level.
level, set FF13, and set FF1
4 and reset part of the memory address space (Figure 2).
Assign an address for the register array 24 to (see a)).

Then, when the chip select signal C5 becomes H level,
A register selection signal 5ELI is output from the AND gate AND3 to the register array 24. Thereafter, read/write access to the register array 24 is started according to the address input to the addressing inputs A0-An.

On the other hand, if it is decoded that a specific address of the register array 24 has been designated, that is, if the specific register address decoding circuit 12 shown in FIG. The output of the AND gate AND2 becomes H level, and
At the same time as resetting the FF 13, the FF 14 is set, and addresses of the memory cell array 23 are assigned to the entire address space (see FIG. 2(a)).

Then, when the chip select signal C5 becomes H level,
A memory selection signal 5EL2 is output from the AND gate AND4 to the memory cell array 23. Thereafter, read/write access to the memory cell array 23 is started according to the address input to the address designation inputs A0 to An.

In this way, when reading/writing to a specific address is performed from the outside, the register array 24 is arranged on the memory map as shown in FIG. 2(a), and it becomes possible to read/write from the outside to the register array 24. .

Also, read/write to a specific register address from outside.
By performing writing, the memory cell array 23 is arranged over the entire memory map as shown in FIG. 2(b), and it becomes possible to read/write from the outside to the entire memory cell array 23.

In the above embodiment, a case has been described in which the FFs 13 and 14 are controlled by the read signal RD, but the write signal WR may also be used, or the logical sum (OR) of the write signal WR and the read signal RD may be used. It may be controlled by

Furthermore, in the above embodiments, the write type of the memory cell array 23 is not particularly limited, but the present invention can be applied to either a static type or a dynamic type.

Further, in the above embodiments, a setting method without multiplexing has been described as an address setting method, but the present invention can also be applied to a memory circuit that sets multiplexed addresses.

〔Effect of the invention〕

As explained above, the present invention provides access to a register group whose address is defined in a part of the memory address space based on a manual read/write control signal for a specific memory address of a memory, or access to a register group for reading/writing to a specific register address of a register group. Since we have provided a switching means that selectively switches access to the memory defined in the entire memory address space based on the control signal, it is possible to arrange the memory in the entire memory address space, and an external circuit for coexistence with the register group is provided. This has excellent effects such as greatly simplifying the process, minimizing program changes due to the mix of register groups and memory, and facilitating software development.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating the configuration of a register/memory switching circuit showing an embodiment of the present invention, FIG. 2 is a schematic diagram illustrating a memory map according to the present invention, and FIG. A circuit block diagram illustrating the configuration of a register selection circuit or a memory selection circuit, FIG. 4 is a configuration block diagram showing an example of a conventional register/memory switching circuit, and FIG. FIG. 3 is a schematic diagram illustrating a memory map of a cell array. In the figure, 1 is a register selection circuit, 2 is a memory selection circuit, 21 is a memory address decoder, 23 is a memory cell array, 24 is a register array, 25 is a functional logic,
26 is an input/output decoder buffer. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) 1. Indication of the case 21. Name of the invention 3. Person making the amendment Registered patent application in 1983 (Spontaneous) No. 196858 Mori switching circuit 5. Invention of the invention in the specification subject to amendment Detailed Explanation Column 6, Contents of Correction (1) "Functional logic 25 controls writing/reading based on C8" on page 4, lines 4-5 of the specification is changed to "C
Writing/reading is performed by 3. ” he corrected. (2) Similarly, change “Specific address” on page 10, line 20 to “
"Specific memory address". (3) Similarly, "Write type" on page 11, line 17 is corrected to "memory cell configuration." Representative 4.

Claims (1)

[Claims] In a memory circuit that allocates a group of registers and memory whose functions are defined in advance in a predetermined memory address space, and performs read/write access of input/output data to the register group or memory in accordance with an input address, access to a register group whose address is defined in a part of the memory address space based on a read/write control signal to a specific memory address of the memory, or access to a read/write control signal to a specific register address of the register group. 1. A register/memory switching circuit comprising switching means for selectively switching access to memory defined throughout an address space.