JPH0245850A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent the unfair copy of program contents by protecting the data output of an EPROM. CONSTITUTION:After a pass-word is written, a power source Vcc of the EPROM is once interrupted. Then, when the power source Vcc is inputted at a time t1', a single pulse is generated as a power-on clear signal POC synchronously with this input. Continuously, at a time t2', a verify mode signal V is generated from a decoder 19 for operation mode selection. At such a time, a verify mode signal V' is the output signal of an AND circuit Z1 for the V and a B+J1.J2. Then, an output signal B is not generated at a blank time. In order to generate the signal of the J1.J2, the data coincidence detecting signal J1 and the address coincidence signal J2 have to be simultaneously generated. Thus, unless an address to be designated as a pass-word address and the pass-word to be written to this address are known, program verify can not be executed in an EPROM writer and unfair reading can not be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a non-volatile semiconductor memory, and particularly to a non-volatile semiconductor memory that prohibits imitation or theft of written programs.

[Conventional technology]

Conventionally, this type of non-volatile semiconductor memory (hereinafter referred to as HPROM)
), programs written in gFROM can be verified, copied, etc. very easily using a BFROM writer.

This makes it extremely easy to imitate and steal programs and data programmed into the BFROM.

For this reason, countermeasures such as those shown in Japanese Patent Application No. 62-220604 have been considered, and since single-chip microcomputers with built-in EFROM do not transmit programs in BFROM to peripheral devices, imitation and plagiarism of programs have been considered. However, when using an E-ROM that transmits a program to a peripheral device, such as a general-purpose BFROM,
In the case of P-OM, since it is used as a program readout element, there is a possibility that the program may be imitated or stolen.

[Problem to be solved by the invention]

In the conventional EPROtM described above, even if the data in the BFROM is completely protected when using a gp OM writer, when transmitting a program to a peripheral device, such as in a general-purpose FSP OM writer, the gFROM must be used. Since the BFROM is used as a data reading element, there is a drawback that the data written in the BFROM may be read, imitated, or stolen. An object of the present invention is to provide a gFROM that can prevent data output by writing an arbitrary password to an address using an EPROM writer or the like. In a non-volatile conductor memory in which data can be written electrically and the data can be erased by ultraviolet rays, a means for specifying an arbitrary specific address as a password writing area and an arbitrary predetermined address for the area are provided. and means for preventing the output of write data by writing the password of #).

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of the first embodiment of the present invention, and FIG. 2 is a circuit diagram of the first embodiment of the present invention.
) to m are timing charts of signals in FIG.

HP shown in FIG. , up to 6-bit,
Address input terminal 33-3 into which the row address of
8, address input terminals 39-47 into which 9-bit column addresses A6-A14 are input, data input/output terminals 23-3°, and data output inhibit circuit 22. It consists of a data write circuit 21 for inhibiting data output.

Data write circuit 21Fi%Al for inhibiting data output.

The column address of λ is connected to the long terminal 48. password·
Write-memory-10, gate circuit 8゜input/output buffer 9, and 15 NMO8) transistor LoS-"l
a e 8 NMo5 transistors Q o = Qγ
have.

The data output prohibition circuit 22 outputs an address match detection signal J,
, a data coincidence detection signal J1 generation section, a blank detection signal B generation section, and a data output control section F.
The generator of the address match detection signal J is composed of 15 NMOs.
8) Insert transistors 0 to 14 and T to Tt4 and 1
5-bit data latch circuit 5.1-bit data latch circuit l.

NOR circuit 2. 15 exclusive OR circuits Go
~Gta.

The data match detection signal J1 generating section consists of eight NM08) transistors P, %P, and Ue to Ut, 8 bits,
Data latch circuit 7.1 bit, Data latch circuit 17. 4.8 exclusive OR circuits He-, H, are included.

The blank detection signal B generating section includes 15 NMOS transistors M.about.M14. 〜几、4、8 NM
O8) Transistors N, ~N, and S.

~8 pins, 23-bit data latch circuit 6°1 bit,
3. Data controller, circuit 3. It has a NOR circuit 18.

The data output control unit F includes an operation mode selection decoder 19
．． 3 AND circuits 2. ．． 2. has.

Next, the operation of this embodiment will be explained. ◎ +1) Data write operation time for inhibiting data output 1.
, when the power supply Vcc is turned on (Fig. 2 (11)
, a power-on clear signal POC, which is a single pulse signal, is automatically generated in synchronization with this, and then at time 1. , a write mode signal W is generated from the operation mode selection decoder 19. This write mode signal W is generated based on the out enable (LJjOE and chip enable signal CB) input to the operation mode selection decoder 19. At this time, a program is written to the memory cell array 13, but a program is not written to the password writing memory 10, but at time ts, the password writing memory 10 is written. If a signal is generated and a write mode signal W is generated here, a program is written into the password/write memory 10.

This password/write signal is not used during normal EFROM usage such as transmitting a program to a peripheral device, for example, when -Vcc voltage is applied to the A140 row address input terminal 47. Assume that the signal is generated when

When the mode signal W and the password writing signal are generated at the same time, a predetermined password is written to the password area at an appropriate address of the memory cell array 13. The address and password of Jin's password are written in the first part. In other words, the password is written in two places: the memory cell array 13 and the password/writing memory lO, and the password writing φ mesori lO , not only the password but also the address of the password written in the memory cell array 13 is written ◇ However, what is written in the password/writing memory lO is NMO8) transistors L0 to L14゜Qo=Q
When the gate of y is turned on, the output signal B is generated, and the blank output signal B is used for writing the password, memory of the memo 910, etc. when the power supply Vcc is turned on.
When all bits in the cell have not been written yet, but even one bit has been written, the B.11W signal is not generated.

Once a password is written in the remote controller memory cell array, writing to the password/writing memory 10 is impossible.

In addition, the write mode signal W' of the password self-writing memory 10 is also the output of the AND circuit Z of B and W, so when the blank output signal B is not generated, it is sent to the password writing memory 10. Even after writing the password, unless the power supply Vcc is turned off once, the blank output signal B can be generated, so that the memory cell array 13. It is also possible to overwrite data in the password/write/memory 10. At time t4, the operation mode selection decoder 19
Verify mode signal ■ generated from B+J1・
The output signal V' of the AND circuit zo of J is the verify signal V'.
When the mode signal V is generated, the blank output No. 1d B is also generated simultaneously, so that the verify mode signal V' is generated. Therefore, it is possible to verify the program and password written to the EPROM.

(2) Program output prohibition operation After the password is written, the power supply Vcc of the EFROM is turned off once, and when the power supply Vcc is turned on at time tl' (Fig. 2 (a)), a single pulse is generated in synchronization with this. A power-on clear signal p o c is automatically generated, and then, when the time reaches i, a verify mode signal V is generated from the operation mode selection decoder 19. This verify mode signal V is the act enable signal OE input to the operation mode selection decoder 19.
and the chip enable signal CB. At this time, the Veri7 eye mode signal V' is V and B+
This is the output signal of the AND circuit z1 of J, .J3, and the output signal B is not generated when blank.

In order to generate the %J, .J2 signal, a data match detection signal Jl and an address match detection signal J are required.

must be generated at the same time, but unless you know the address specified as the password area and the password written to this address, it is impossible to verify the program with the FROM writer.

At time 11", after the power supply Vcc is turned on, at time t2
Even if the output mode signal OUT is output from the operation mode selection decoder 19 in
If the user does not know the password and the address where the password is written, it is impossible to generate the Jl/J signal and it is impossible to output the data in the EPROM to the outside.

(3) Program output prohibition release operation time t! 'When the power supply Vcc rises, the power is turned on.
Clear signal POC is generated, and at this time gate circuit 8 and input/output buffer 9 are not in data output mode (NMO8).
By turning on the gates of the transistors M0 to M K4 m N6 to N7, the data written in the password writing/memory 10 is latched into the data latch circuit 6. 2) As mentioned in the program output prohibition operation, time t! ', when program output is prohibited, generates the I-W signal at time t3, and enters the address and password write mode of
MO8) Turn on the gates of transistors PO and P, and swath the data latch circuit 7.

Latch the data. At this time, at the same time, the NMOS transistor is set to 1. When the gate of ONL is ONL, the data-latch circuit 5 is checked when the address power error of the word (sword) is detected.

When the W+V+OUT signal is generated, it is detected (by the exclusive OR cycle Wb Ho -Hv) whether the password has been input correctly, and if it has been input correctly, a data match detection signal J1 is generated.

Also, at the same time, exclusive or times Wt G o -0
14, it is detected whether the password address has been entered correctly manually, and if it has been entered correctly, a data match detection signal J2 is generated. In this way, if the password and password address match at the same time, J
l・J, a signal is generated.

The verify mode signal V' is the output signal of the AND circuit z1 of the generated signal V from the operation mode selection decoder 19 and B+J, .J2.
and Jl/J: When the signals are generated at the same time, the verify mode signal V' is generated, and verification with the EFROM writer is possible. - The output mode signal OUT' is also generated in exactly the same way, and when the I/W signal is generated, Enter the password address at address input terminals 31-47. By inputting multiple passwords to the data input/output terminals 23 to 30, only when the password address and password are input correctly, the data controller, child circuit 1, and data latch circuit 17 are
It is possible to check the “High” data!+
It is possible to set lB+J, .J, = @H@, and it is possible to cancel the program output prohibition by making the output mode signal OUT' greater than or equal to 0, which makes it possible to generate the output mode signal OUT'.

However, when this I-W signal is generated, NMO8) transistor L
Since there is no O-Lsa e Qo-Qy's riONL, data will not be overwritten in the password-writing memory 10. If the address and password are entered and the data is incorrect, the memory cell array 13 can overwrite the data. It is also possible to change the data written in the EFROM.

When actually writing the password to the HP OM of the present invention,
Since the password writing area may also be used as a program or data transmission area to peripheral circuits, data can be written to the memory cell array 13 in the same manner as in general BFROM, after writing the password. By determining the address of the memory cell array 13 and using the data written at that address as a password, the password address and the password are stored in the password/write memory IO. When writing data, it is possible to write data in exactly the same way as a general gFROM without having to worry about the password address or password data. In this case, the password address and password input when powering up the power supply Vcc will be automatically input by IIY input, data input from a microcomputer, etc., input from an external storage device such as a magnetic desk or IC card, etc. It is also possible to configure the system so that the password address and password data are input only when the power supply Vcc is turned on, and the entire system including the BFROM of the present invention or the main g of invention
Once the power supply Vcc of the FROM is turned on and the password address and password are entered manually, it is possible to use the FROM without being aware of the password unless the power supply Vcc is turned off.

FIG. 3 is a circuit diagram of a second embodiment of the present invention, and only the parts different from FIG. 1 will be explained.

The difference between FIG. 1 and FIG. 3 is that an input mode signal IN is newly added to the decoder for operation mode selection, and a write mode signal, which is an output signal from the decoder for operation mode selection, is sent to the human output buffer 15. The signal W, the verify mode signal ■, and the output mode signal OUT are directly input as they are, and NMOS transistors D and -D are added between the data input/output terminals 23 to 30 and the human output buffer 15. When the program prohibition is canceled using the circuit configuration shown in Figure 3,
Input mode signal IN from the operation mode selection decoder 19
This is possible by generating a password and then entering the password address and password.

In addition, if only the write mode signal W is used, the gates of NMO8) transistors Do-D are not ONL, so not only the password/write memory 10 but also the data of the memory cell array 13 cannot be overwritten. If the password address and password are input incorrectly, overwriting of data in the memory cell array 13 can be avoided.

Furthermore, by changing each input signal as shown below, not only does the circuit for generating the password writing signal I, which requires a special circuit configuration, become unnecessary, but when the program prohibition is canceled, Since it is not necessary to generate the write mode signal W, which is a signal generated during operation, the gpaoM write voltage Vl)
There is no need to apply f).

In the case of the first embodiment, a person who does not know the password
4. If an incorrect password address and password are entered, data will be overwritten in the memory cell array 13. Destroy the data in the BP OM. Therefore, the effect of prohibiting imitation and theft of data in the EPROM is extremely large.

In the second embodiment, even if a person who knows the password enters the password incorrectly, the NM
O8) The transistors Do to D are not turned on, and data is not overwritten in the memory cell array 13.
gpI (loM data is not destroyed. Therefore, even if someone who knows the password inputs the password manually by mistake, the data is protected.

If there is an error in the password address or password, either add a circuit that overwrites the memory cell array 13, or add a circuit to the data input/output terminal.
The gates of MOS transistors D, ~D7 are semi-permanently turned off.
EPRO by adding a circuit that prevents
It is also possible to block data output within M.

〔Effect of the invention〕

As explained above, the present invention protects the output of gPROM data, thereby making it impossible to check the program contents and making it easier to protect the copyright of the program. Furthermore, a person who knows the password can easily remove this protection and use it in the same way as gFROMs currently on the market.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of the first embodiment of the present invention, Fig. 2(a)
~- is the signal timing chart in Figure 1, and Figure 3 is the timing chart of the signal.
The figure is a circuit diagram of the second embodiment of the present invention. 6...
15 bits, data for G, circuit for CH, 7...8 bits,
Data latch circuit for gate, 8, 14... Gate circuit, 9.15... Input/output cover y 77.10...
...Password writing memory, 11... Column decoder, 12... Row decoder, 13...
... Memory cell array, 19 ... Decoder for operating mode selection, 21 ... Data write circuit for prohibiting data output, 22 ... Data output prohibition circuit,
23-30... Data person output terminal, 31-48
・・・・・・Address input terminal A, 〜persontS・・・・・・Address, vCC・・・・
・Power supply, POC...Power on clear signal, w
, w'... Light mode signal, v, v'...
...Verify mode signal, OUT, OUT'...
...Output mode signal, J.・・・・・・Data controller, output signal of child circuit 17, J3・
... Data controller, output No. 16 of child circuit 1, Ko% is 14. L. 〜L7・M・〜M14・N・〜N、、P・〜P7-QO
~Q7・R,%R,4・S・〜S7・T o = T
t4・U. ~U,...NMO8) transistor, zo~Z snow...AND circuit, H6-Hy, G...G14
・・・・・・Exclusive OR circuit, D・〜D・
...-, NMO8) transistor, IN...Input mode signal. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] In a non-volatile semiconductor memory in which data can be written electrically and the data can be erased by ultraviolet rays, means for specifying an arbitrary specific address as a password writing area, and an arbitrary password predetermined for the area A non-volatile semiconductor memory characterized by comprising: means for blocking output of the write data by writing the write data.