JPH0245852A - Loop scan circuit - Google Patents

Abstract

PURPOSE:To improve the use efficiency of a loop scan memory and to shorten the processing time of a system by parallelly executing the loop scan operation of an I/O processor and the internal operation of the I/O processor. CONSTITUTION:For the loop scan operation of an I/O processor 1, the address of a loop scan memory 5 is set from a DB to a counter 4 and the latch value of a channel device 2 is written and read. For the internal operation of the I/O processor 1, data are written and read to the loop scan memory 5 in correspondence to the address value, which is set to an address register 3. Since the speed of the shift operation of loop scan is lower than that of the internal processing operation, the access of the memory 5 is executed by a high speed clock for internal processing and the access processing of the loop scan is operated by the above mentioned clock. On the other hand, the internal processing is executed with timing excepting for a case that the above mentioned access processing is executed.

Description

Detailed Description of the Invention [Summary] Regarding a loop scan circuit configured across two devices in a channel processor, for example, an I/O processor (IOP) and a channel device (CHE), In order to reduce the processing time of the system, we aim to provide a loop scan circuit that performs external access and internal access in parallel, and allows external and internal processing to operate independently of each other. A loop scan circuit configured to span between an I/O processor and a channel device in a processor, the loop scan circuit having a circuit for writing/reading scan data and performing a loop scan operation in the I/O processor. A loop scan memory and an I10 used for internal processing of the I10 processor and for protecting each other's memory addresses.
A processor-dedicated address register and a counter register connected in parallel with the address register for loop scan operation to protect each other's memory addresses, and both the I10 processor and the channel device use the loop scan memory. In this case, the loop scan memory is operated at a faster cycle than the loop scan shift operation of the channel device, and the I10 processor utilizes the loop scan memory during the remaining time when the loop scan is not performed. The address register is configured to perform other internal processing operations.

[Industrial application field]

Regarding the loop scan circuit configured between two devices in the channel processor, for example, the I10 processor (IOP) and the channel device (CHE), especially in the method of using the loop scan memory, The loop scan memory can be used freely from within the I/○ processor in parallel with writing/successive access to the loop scan memory, so that the loop scan memory does not affect each other's processing internally and externally. Regarding scan circuits.

[Prior art and problems to be solved by the invention] FIG. 4 is a block diagram of a conventional loop scan circuit. L
SM is a loop scan memory, CNT is a counter register, BRG is a buffer register, and WRG is a write register, which are provided in the IOP. CH
There is also a latch register L in E for loop scanning.
is provided in a loop shape. These latches are connected to the IOP.

The purpose of loop scan is to arbitrarily write/output the CHE latch value during testing or in the event of a failure. Conventional loop scan memory operates with an external clock cycle and cannot be accessed from the outside. During the process, the loop scan memory is occupied only by that operation, and access from internal circuits is suspended.

That is, as shown in the figure, the conventional loop scan circuit is
The address of the loop scan memory is set in the counter CNT from the data bus DB via the buffer register BRG, and data in the loop scan memory is written/output one after another.

However, since the address of the loop scan memory is specified only by the counter register, other internal accesses to the loop scan memory cannot be processed while the loop scan operation is being performed, making it difficult to effectively utilize the loop scan memory. As a result, internal operations were delayed and the actual processing speed of the system was also delayed.

An object of the present invention is to improve the usage efficiency of loop scan memory so that external access and internal access can be performed in parallel, so that processing operations can be performed independently of each other, in order to reduce system processing time. The object of the present invention is to provide a loop scan circuit that can perform the following steps.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle configuration of the present invention. As shown in the figure, according to the present invention, there is provided a loop scan circuit configured astride between an I10 processor (IOP) in a channel processor and a channel device (CHE),
10 processor includes a loop scan memory (LSM) for writing/reading scan data and performing a loop scan operation, and a 110 processor used for internal processing of the I10 processor to protect each other's memory addresses.
It includes an address register (ARG) for the processor world and a counter register (CNT) connected in parallel with the address register for roof scan operation to protect each other's memory addresses, and is used for both the I10 processor and the channel device. When using the loop scan memory, the loop scan memory is operated at a faster cycle than the loop scan shift operation of the channel device, and the I10 processor performs the loop scan during the remaining time when no loop scan is performed. The present invention is characterized in that other internal processing operations are performed by the address register using memory.

[For production]

In such a configuration, the external clock cycle is originally longer than the internal clock cycle, and since the loop scan memory can also be operated by the internal clock,
External scan access processing is operated in accordance with the internal clock cycle, the processing is completed within one loop scan cycle, and other internal processing is also performed within that one cycle.

Therefore, in order to protect each other's memory addresses, an address register for internal processing and a counter register for scan operation are provided. According to the present invention, the processing speed of the system can be improved by realizing simultaneous processing of an external scanning operation and an internal operation.

〔Example〕

FIG. 2 is a block diagram of a loop scan circuit according to an embodiment of the present invention. As shown in the figure, an address register ARG for internal processing and a counter register CNT for scan operation are provided in the IOP in parallel with the data bus DB. The channel family [CHE is the side that is subjected to the loop scan, and the I10 processor IOP is the side that takes in the loop scan. In the CHE, latches L (Ll to Ln) are connected in a loop for loop scanning, and both ends thereof are connected to the IOP.

During loop scan operation, this loop is used to shift the data in the latch one stage at a time and pass the data to the IOP.
The IOP receives the data and proceeds with processing. That is, I
On the OP side, write register 5T via register 5TGO
The value is taken into the GI, then into the loop scan memory LSM, and the value is returned to the CHE via the register 5TG2.

In this case, the present invention changes the clock period in the IOP to CH
The clock cycle is made shorter than that in E, and the clock cycle is operated on the IOP side.

That is, in the past, everything within the same loop was operated at the CHE scan clock cycle, but in the present invention, even within the same scan loop, the clock cycles are different between the IOP side and the CHE side.

Since the clock cycle within the IOP is sufficiently shorter than the clock cycle for scanning the CHE, the CHE scan operation on the IOP side can be completed with sufficient margin within one CITE scan cycle, and the remaining time is used to perform other operations on the IOP side. Processing operations can be performed.

The method of scanning CHE is to shift one bit at a time, and write to the LSM one bit at a time.

The address of the loop scan memory is first set in the loop counter CNT, and is decremented one by one) (-
1) and is written to the indicated address. On the other hand, on the IOP side, it is possible to process arbitrary data in a 32-bit width by giving a memory address each time.

In this way, a new address register ARG is provided so that the IOP can freely set an address, and is made independent of the scan address.

FIG. 3 is a timing chart of the clock signal of the configuration shown in FIG. l0P-CLK is a clock that operates the IOP, and CHE-CLK is a clock that operates the CHE. When scanning the CHE, the timing is four times that of the normal operation of the CHE.

Bnable Loop 5hift from IOP (
When the E L S ) signal appears, CHEl, :l;! -A
-CLK and +B-CLK are sent and a loop scan is started.

A normal sample operation is performed between -A-CLK and +B-CLKO, and a hold operation is performed from +B-CLK to -A-CLK. -A-CLK passes data to 5TGO of IoP, and after 5TGO1,:f- evening arrives, IOP
The clock progresses through 5TGI and LSM to 5TG2.

Then, data is passed from 5TG2 to CHE using +B-CLK. In this way, the difference in clocks between IOP and CHE is covered.

In actual use, in addition to IOP and CHE, there is a clock oscillator CLKA (not shown) that generates the A clock, and when IOP outputs the ELS signal to CLKA, CLK
A is designed to send -A-CLK and +B.CLK to CHE. In this case, the clock must be -A・CLK
Sent from At the timing when CLKA sends -A-CLK to CHE, it sends the same signal to IOP, and IO
This -A-CLK is converted into a 1τ signal on the P side.

As explained above, l0PI-! When all operations are performed by l0P-CLK and a loop scan is performed, the loop scan operation uses the LSM only during the timing when the LSM is occupied during the loop scan indicated by "T II" in the timing chart. At other timings, it corresponds to the request inside the IOP.In this case, the switching when the loop scan occupies the LSM is -A-C
This is done when the LK IOP/1τ signal comes to 5TGI. The LSM address selects the counter side only at this timing, and selects the address register side at other timings. 5 Set the loop out data at the timing of TG2.

〔Effect of the invention〕

As described above, according to the present invention, the time that the loop scan of the channel device occupies the inside of the I10 processor is reduced, and the IOP request can be executed during the other time in one cycle, so that the system The actual processing speed will be significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram of the principle configuration of the present invention, FIG. 2 is a loop scan circuit diagram of an embodiment of the present invention, FIG. 3 is a timing chart of the clock signal of the circuit in FIG. 2, and FIG. FIG. 2 is a conventional loop scan circuit diagram. (Explanation of symbols) IOP...I10 processor, CHE...channel device, SM...loop scan memory, ARG...address register, CNT...counter register, 5TGO, 5TGI, 5TG2...・Register, DB・
・Data bus

Claims (1)

[Claims] 1. I/O processor (IOP) in the channel processor
) and a channel device (CHE), the I/O processor includes a loop scan memory for writing/reading scan data and performing a loop scan operation. (LSM), an address register (ARG) dedicated to the I/O processor used for internal processing of the I/O processor and for protecting each other's memory addresses; and a counter register (CNT) for loop scan operation to protect addresses, and when the loop scan memory is used in both an I/O processor and a channel device, the loop scan memory is used in the loop scan operation of the channel device. The I/O processor operates at a faster cycle than the shift operation of the scan, and the I/O processor uses the loop scan memory to perform other internal processing operations with the address register during the remaining time when the loop scan is not performed. A loop scan circuit characterized by