JPH0245932A - Passivation structure in semiconductor device - Google Patents

Abstract

PURPOSE:To prevent fluctuation of resistance by accumulating a silicon layer in contact with a protection insulation layer covering the substrate surface where a semiconductor circuit including a polycrystal silicon film resistance element is formed. CONSTITUTION:An interlayer insulation layer 2 is formed on a semiconductor substrate 1 and a resistance element 3 consisting of polycrystal silicon film is formed on the interlayer insulation layer 2. A protection insulation layer 5 is formed on the resistance element 3 and a nitriding silicon film 6 for passivation is formed on the entire surface of the insulation layer 5. A polycrystal silicon layer 10 is provided between the resistance element 3 and the nitriding silicon film 6, thus shutting off hydrogen which permeates the insulation layer 5 from the nitriding silicon film 6 in the heat treating process and is trapped by a polycrystal silicon film resistance element. No hydrogen is trapped by the polycrystal silicon film, thus preventing resistance of resistance element from fluctuating.

Description

[Detailed Description of the Invention] [Summary] This invention relates to passivation for protecting semiconductor circuits from moisture, etc.

The purpose is to prevent hydrogen from becoming trapped in polycrystalline silicon film resistance elements that make up semiconductor circuits, causing changes in characteristics.

A silicon layer is deposited in contact with a surface of a protective insulating layer covering a substrate surface on which a semiconductor circuit is formed.

[Industrial application field]

The present invention relates to passivation for protecting semiconductor circuits from moisture and the like.

[Conventional technology]

As one type of package for a semiconductor device, a substrate (chip) on which a semiconductor circuit is formed is molded in resin. A so-called plastic package is used. In this case, as passivation for protecting a semiconductor circuit formed on a silicon substrate or the like from moisture etc., the entire upper surface of the substrate is generally covered with a silicon nitride film and then molded. Silicon nitride films are widely used because they have high moisture resistance (and can be formed at a temperature below the melting point of aluminum, which constitutes the wiring of semiconductor circuits.) Formation of silicon nitride films by CVD using ordinary thermal decomposition is as follows: It is necessary to carry out at a temperature of 800℃ or higher, but 4
Plasma C
The VD method is used.

[Problem to be solved by the invention]

On the other hand, resistive elements made of polycrystalline silicon films are sometimes used in semiconductor circuits. Figure 4 is.

1 is a cross-sectional view of a main part showing an example of a conventional passivation structure in a semiconductor device having the polycrystalline silicon film resistance element, in which an interlayer insulating layer 2 is formed on a semiconductor substrate 1 such as a silicon chip.

A resistive element 3 made of a polycrystalline silicon film having a predetermined shape and size is formed on the glabellar insulating layer 2. The resistor element 3 is doped with an impurity such as phosphorus (P) during or after the process of depositing the polycrystalline silicon film constituting the resistor element 3.
It is adjusted to have a predetermined sheet resistance. As shown in the figure, a polycrystalline silicon film resistance element 3 is connected to a diffusion layer 4 formed in a semiconductor substrate 1 through a contact hole provided in, for example, an interlayer insulating layer 2 .

A protective insulating layer 5 made of, for example, borosilicate glass (PSG) is formed on the polycrystalline silicon film resistance element 3.
Further, a silicon nitride film 6 for passivation is formed over the entire surface of the protective insulating layer 5. In addition, in Figure 1,
Reference numeral 7 indicates a wiring made of aluminum for internal connection of the semiconductor circuit.

By the way, the silicon nitride film 6 formed using the plasma CVD method as described above contains hydrogen. The amount may reach 1, for example, 20% (molecular number ratio). This hydrogen passes through the PSC protective insulating layer 5 and is trapped in the polycrystalline silicon film resistance element 3 in the subsequent heat treatment step 1, for example, an annealing step performed after bonding external wiring such as an aluminum wire to the semiconductor circuit chip. As a result, the resistance value of polycrystalline silicon film resistance element 3 generally decreases.

The above phenomenon is considered to be first-order. First, in plasma CVD, 5iH4 (silane), which is one of the raw material gases for forming the silicon nitride film 6, dissociates to generate radicals such as +SiH3'', 5in2'', and SiH'', which are converted into silicon nitride. NH, which is the other raw material gas, is incorporated into the film as it grows.
The same applies to 3 (ammonia). In this way, silicon nitride film 6 contains a large amount of hydrogen (H).

On the other hand, a portion of the #(P) implanted into the polycrystalline silicon film constituting the resistance element 3 as described above is bonded to dangling bonds on the surface of the crystal grains of the polycrystalline silicon film.

However, when the hydrogen in the silicon nitride film 6 diffuses to the polycrystalline silicon film resistance element 3 in the heat treatment process as described above, this hydrogen replaces the phosphorus (P) atoms bonded to the dangling bonds. As a result, the free P atoms diffuse into the polycrystalline silicon particles, increasing the impurity concentration, and as a result, the resistance value of the resistance element 3 decreases.

Since the above-mentioned change in resistance value varies due to variations in heat treatment conditions, it becomes difficult to control the resistance of polycrystalline silicon film resistance element 3 to a predetermined value.

An object of the present invention is to prevent variations in the resistance value of the polycrystalline silicon film resistance element 3 due to hydrogen diffused from the silicon nitride film 6.

[Means to solve the problem]

The above object is achieved by a passivation structure in a semiconductor device according to the present invention, characterized in that a silicon layer is deposited in contact with the surface of a protective insulating layer covering a substrate surface on which a semiconductor circuit is formed.

[For production]

Another silicon layer is interposed between the polycrystalline silicon film resistance element and the silicon nitride film to block hydrogen passing through the protective insulating layer made of PSG or the like. Since the silicon layer has excellent moisture resistance, it can itself be used as a passivation film. Therefore, a passivation structure is provided in which a silicon layer is deposited over the entire surface of the PSG protective insulating layer instead of the silicon nitride film.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

In the following drawings, the same parts as in the existing drawings are designated by the same reference numerals.

FIG. 1 is a sectional view of a main part showing an embodiment of the passivation structure of the present invention, and the materials, structures, and formation conditions of the parts indicated by numerals 1 to 7 are the same as the corresponding parts in FIG. 4. .

In FIG. 1, a polycrystalline silicon layer 10 with a thickness of about 0.1 μm is provided between a polycrystalline silicon film resistance element 3 and a silicon nitride film 6. As shown in FIG. In the figure, the polycrystalline silicon layer 10 has a structure embedded in the protective insulating layer 5, but this is because, for example, in the step of depositing the protective insulating layer 5 by the CVD method, raw material gas is used to generate the silicon layer. This can be easily implemented by temporarily switching to a gas of

The polycrystalline silicon layer 10 is formed using SiJ, (disilane)
Alternatively, 5iJe (disilane) is used as the raw material gas.

This is carried out by the CVO method, which utilizes a thermal decomposition reaction under reduced pressure. By using these raw material gases.

500°, well below the melting point of aluminum wiring, 660°C
Polycrystalline silicon layers can be produced at temperatures of C and below. Furthermore, since thermal decomposition reaction CVD is used, active radicals are not generated and hydrogen is not stored in the polycrystalline silicon layer 10. Examples of conditions for forming each layer or film and subsequent annealing conditions are shown below.

■Polycrystalline silicon film resistance element 3 Raw material gas: 5i) I4 (silane), total pressure: 1To
rr.

Generation temperature = 620°C, phosphorus (P) doped.

Membrane resistance: 4000 Ω/port■psc protective insulating layer 5 Raw material gas: 5iHt+PIh +Q□, total pressure: total pressure:
Atmospheric pressure generation temperature: 42 layers ■10 polycrystalline silicon layers Raw material gas: 512H&+ Total pressure: 5 Torr.

Generation temperature: 400℃ ■Silicon nitride film 6 Raw material gas: 5iJ6, total pressure: ITorr.

Generation temperature: 1 Torr, Plasma CVD ■ Annealing conditions Temperature: 2500° C., Atmosphere: atmospheric pressure Nitrogen If the polycrystalline silicon layer 10 is not provided, the film resistance of the polycrystalline silicon film resistance element 3 is increased to the initial value of 4000 Ω/cm by the above annealing. Although it drops to 1000Ω/mouth from the mouth. When a polycrystalline silicon layer 10 is provided.

Even after the above-mentioned annealing, the resistance is 3700 Ω/hole, which can be considered constant within the error range.

FIGS. 2 and 3 are sectional views of main parts showing another embodiment of the passivation structure of the present invention.

The materials, structure and forming conditions of the parts designated by numerals 1 to 7 are the same as the corresponding parts in the above embodiments.

Regarding the effect of preventing hydrogen diffusion from the silicon nitride film 6,
Polycrystalline silicon layer 10 does not necessarily have to be embedded in protective insulating layer 5. Therefore, in the structure shown in FIG. 2, the polycrystalline silicon layer 10 is provided on the protective insulating layer 5, and the polycrystalline silicon layer 10 as shown in FIG.
There is no protective insulating layer 5 between O and the silicon nitride film 6.

The structure shown in Fig. 2 is obtained by forming a polycrystalline silicon layer 10 by the CVO method under the same conditions as above, and then changing the raw material.
This is possible by immediately forming the silicon nitride film 6.

It is known that the silicon layer has excellent moisture resistance.

Furthermore, a silicon layer that is not doped with impurities has a high resistance comparable to that of an insulating layer. Therefore, passivation is possible without forming a silicon nitride film thereon. FIG. 3 shows a structure in which after a polycrystalline silicon layer 10 is formed on the protective insulating layer 5, a silicon nitride film 6 is not formed as in the previous embodiment. This is the fourth
This corresponds to the case where a silicon layer 10 is formed in place of the silicon nitride film 6 in the structure shown in the figure. silicon layer 1
0 can be produced using the CVD method using a thermal decomposition reaction as described above, and therefore does not cause the problem of resistance change with respect to the polycrystalline silicon film resistance element 3 such as the silicon nitride film 6. Moreover, its formation temperature is about 400° C., which is the same as that of the silicon nitride film 6.

In fact, the formation rate is higher than that of the silicon nitride film 6. This is advantageous in terms of shortening the manufacturing process.

〔Effect of the invention〕

According to the present invention, it is possible to reduce the change in resistance value of a polycrystalline silicon film resistance element in a semiconductor device, improve the reproducibility and stability of the characteristics of the semiconductor device, and improve the manufacturing yield.

5 is a protective insulating layer.

6 is a silicon nitride film.

7 is aluminum wiring.

10 is a silicon layer It is.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of essential parts showing an embodiment of the passivation structure of the present invention. FIG. 2 and FIG. 3 are main part sectional views showing another embodiment of the passivation structure of the present invention. FIG. 4 is a sectional view of a main part showing an example of a conventional passivation structure in a semiconductor device having a polycrystalline silicon film resistance element. In fig. 1 is a semiconductor substrate. 2 is an interlayer insulating layer. 3 is a polycrystalline silicon film resistance element. 4 is a diffusion layer.

Claims (1)

[Claims] A passivation structure for a semiconductor device, characterized in that a silicon layer is deposited in contact with the surface of a protective insulating layer covering a substrate surface on which a semiconductor circuit is formed.