JPH0246074A - Filter circuit - Google Patents

Abstract

PURPOSE:To avoid the generation of a ringing by storing and holding the start point of an effective signal in an input signal, detecting the DC offset of the input signal, subtracting this from the input, removing the DC offset and after that, inputting it to a filter. CONSTITUTION:A selector 2 selects the output signal of a latch 3 in the timing of a start point t1 of the slope part of an input signal Si, that condition is maintained and a storage value is outputted continuously until the timing of an end point t2 of the slope part. Consequently the DC offset is removed from an output signal Sk=Sid-Sj of a subtracter 6 and the signal from which the DC offset is removed is inputted to a filter 11. A selector 7 selects an output signal Sm of a latch 8 in the timing of the end point t2 and an output signal Sk of the subtracter 6 at the t2 is stored by the latch 8. Thus, the output signal Sm of a second storage circuit 9 keeps a fixed value after the end point t2 and therefore, the ringing is not generated in the output of the filter 11 at the end point t2.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a filter circuit, and particularly performs filter processing on an input signal in which an effective signal exists intermittently during a specific period. Related to filter circuits.

(Prior Art) One of the video signal recording methods in a VTR is to divide the video signal for one field into tracks of multiple channels.
There is a multi-channel division recording method that divides and records data. When such a recording method is used, image quality deterioration due to differences in characteristics such as level, gain, linearity, etc. between channels becomes a problem. As a circuit to correct this image quality deterioration, Dynamic
A Level & LInearlLyCorrecLor circuit (hereinafter referred to as a DLC circuit) is known.

In this DLC circuit, for example, National Tech
nicalRoport Vol, 32 No, 4 A
As described in UG, 198B, P, 425-42B, a reference ramp signal that covers from the black level to the white level of the video signal within one horizontal scanning period is inserted into the vertical blanking period of the video signal. Record. This reference ramp signal is, for example, a digital signal having a slope of 250 steps from 0 to 255 when the number of quantization bits of the video signal is 8 bits. Since we know the level at the time of recording that corresponds to the position on the time axis of the reproduced reference lamp signal (hereinafter referred to as the reproduced lamp signal), we can reproduce the conversion that corrects the distortion that the reproduced lamp signal has undergone. When applied to video signals, image quality deterioration caused by differences in characteristics between channels is corrected.

In such an LC circuit, the reproduced lamp signal is averaged over several fields in order to improve the S/N, and is further processed by a smoothing filter. The smoothing filter is a type of low-pass filter, and one with fairly steep characteristics is used. The step response of this smoothing filter is shown in FIG. As shown in the figure, the output of the smoothing filter produces ringing around the point where the input changes stepwise.

The reference lamp signal used in the DLC circuit is shown in Figure 4 (a).
The waveform is as shown in t1 to t2, which is the ramp part.
The level of the slope part during the period increases by one quantization step. In this case, the ringing effect shown in FIG. 3 should not appear for more than one quantization step. If there is a step-like change on the slope of the +Jj raw ramp signal that causes ringing, it will be detected by dropout detection, S/N judgment, etc., and the reproduced ramp signal will be processed by the DLC circuit. Use as data for correction conversion is refused.

Incidentally, in the DLC circuit, a RAM is used as a circuit for averaging the reproduced lamp signals.

If this RAM has a capacity that can store only the slope part of the reproduced ramp signal, and the values of the parts other than the slope part are set to zero, the signal led from the averaging part to the smoothing filter will be as shown in Figure 4(b). The waveform becomes as shown, and the waveform suddenly falls at the end point t2 of the slope portion. Therefore, the output waveform of the smoothing filter is shown in Figure 4 (
As shown in d), ringing occurs at the end point t2 of the slope portion, and its influence extends to the trailing edge of the slope portion. When such ringing occurs in the output signal of the smoothing filter, there is a problem that the corrective conversion of the DLC circuit cannot be performed correctly.

In order to prevent ringing from occurring in the output waveform of the smoothing filter at the end point t2 of the slope portion of the reproduced ramp signal, the reproduced ramp signal including the portions before and after the slope portion is added in an averaging section before the filter. Although averaging is sufficient, the RAM capacity of the averaging section increases accordingly. In other words, the number of data in the slope part of the ramp signal is usually on the east side of the power of 2 (for example, 28-256 if the number of quantization bits is 8 bits, 29-512 if the number of quantization bits is 9 bits), and it is very difficult to quantize due to the structure of the RAM. Selected based on good numbers. The fact that the arithmetic averaging section performs arithmetic averaging including the parts before and after the slope part means that a slight data loss is added before and after the slope part. R required when
A device with twice the capacity of AM will be used, and R
This results in the AM address counter also increasing.

On the other hand, if a DC offset occurs in the video signal during recording/playback, the signal input to the smoothing filter will have a waveform as shown in Figure 4 (C), and the output signal of the smoothing filter will have a waveform as shown in Figure 4 (e). ), and ringing also occurs at the starting point tl of the slope portion.

(Problem to be Solved by the Invention) As described above, in the conventional technology, when an input signal in which a valid signal such as the slope part of a ramp signal is intermittently present during a specific period is processed by a filter with steep characteristics, , if only valid signals are input to the filter, or if the filter input signal contains a DC offset, ringing may occur in the filter output signal if there is a large step change in the filter input signal. There is a problem that occurs.

Furthermore, if a signal including both before and after the effective signal is inputted to the filter, there is a problem that the circuit scale of the averaging section using the RAM increases, which is disadvantageous for integration.

In the present invention, only effective signals that exist intermittently during a specific period are input, and as in the case where the input signal has an offset, there is a step-like change with a large amount of integration before and after the effective signal period of the input signal. An object of the present invention is to provide a filter circuit in which ringing does not occur in an output signal even when

[Structure of the Invention] (Means for Solving the Problems) The filter circuit according to the present invention stores the value of the starting point of the effective signal of the input signal and outputs the stored value at least during the existence period of the effective signal. , a first storage means that outputs the input signal as it is during other periods, a subtraction means that subtracts the output signal of the first storage means from the input signal, and a subtraction means that determines the end point of the effective signal in the output signal of the subtraction means. The input signal is supplied to the filter through the storage means of TS2, which stores a value and outputs the stored value for a predetermined period of time, and outputs the output signal of the subtraction means as it is at least during the existence period of a valid signal of the input signal. . Furthermore, adding means is provided for adding the output signal of the filter and the output signal of the first storage means, and the output signal of this adding means is taken out as the final output.

(Operation) Since the stored value of the first storage means corresponds to the DC offset of the input signal, this DC offset is subtracted from the input signal to remove the DC offset at the filter input end,
Also, the D output from the first storage means is added to the output of the filter.
By adding the C offset again, ringing due to a step change in the input of the filter due to the DC offset is avoided.

-b1 By storing the value of the end point of the effective signal using the second storage means and inputting it to the filter, the effect of ringing at this end point is moved beyond the period of existence of the effective signal, and the output of the filter is Doesn't appear.

In this way, in the filter circuit of the present invention, even if the input signal is only an intermittently present effective signal and includes a DC offset, the output signal has the starting and ending points of the effective signal of the input signal. No ringing occurs due to step-like changes in .

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram showing a filter circuit according to an embodiment of the present invention, and FIG. 2 is a signal waveform diagram of each part of FIG. 1.

In FIG. 1, an input terminal 1 receives, for example, a digital input signal St quantized to about 8 bits. This input signal Sl is obtained by converting, for example, the ramp signal shown in FIG. For example, as shown in FIG. 2, this is a digital signal that corresponds to a ramp signal in which only a slope portion is intermittently present as an effective signal and has a DC offset. .

This input signal S1 is supplied to the first
is led to one input terminal of the selector 2 in the storage circuit 4 of the . . The output signal of the selector 2 is guided to the latch 3, and the output signal Sj of the latch 3 is guided to the other input terminal of the selector 2. The selector 2 selects two input signals Si and S based on the select signal 5ELL supplied from the control circuit 10.
Selectively output one of j.

The input signal SI is also input to a latch 5, whose output signal Sid is led to one input of a subtracter 6.

The output signal Sj of the first storage circuit 4 is introduced to the other input terminal of the subtracter 6. The latch 5 is used to compensate for the delay time caused by the latch 3 in the first storage circuit 4 and to synchronize the timings of both input signals Sid and Sj of the subtracter 6.

The output signal Sk (=Sld-Sj) of the subtracter 6 is guided to one input terminal of the selector 7 in the second storage circuit 9 consisting of the selector 7 and the latch 8.

The output signal of the selector 7 is guided to the latch 8, and the output signal Sm of the latch 8 is guided to the other input terminal of the selector 7.

The selector 7 selectively outputs one of the two input signals Sk and So+ based on the select signal SEI, 2 supplied from the control circuit 10.

The output signal SIl of the first storage circuit 9 is guided to the filter 11. This filter 11 is a low-pass filter consisting of a digital filter described in the above-mentioned known literature, etc., and the input signal Sm is delayed by a shift register consisting of latches 12-15. The input signal SrA of the latch 12 and the output signal of the input gate 15 are added by the adder 16, and further by the multiplier 18 by the tap coefficient "-3".
” and then led to one input terminal of the adder 21.

The output signal of latch 12 and the output signal of latch 14 are added by adder 17 and further multiplied by a tap coefficient "12" by multiplier 19, and then guided to the other input terminal of adder 21. The output signal of Matau Sochi 13 is multiplier 2
After being multiplied by tap coefficient "17" by 0, the adder 22 adds the signal to the output signal of the adder 21 . The output signal of the adder 22 is divided by the divider 23 into r l/35J
The output t of the filter 11 is multiplied by t, and becomes the output t of the filter 11. The frequency characteristics of this filter circuit 11 are expressed by the following equation.

-3(Z-"+22)1 The output signal Sn of this filter 11 is guided to one input terminal of the adder 24. The output signal Sj of the first storage circuit 4 is also guided by the latches 25 to 27. After being delayed by the delay caused by latch 812.13 from subtracter 6 to the main tap of filter 11 (in this example, the output terminal of latch 13), it is guided to the other input terminal of adder 24.

Note that the control circuit 10 determines the start point tl and end point t of the slope portion based on a synchronization signal included in the input signal Sl, for example.
2 is detected, and based on that, the select signal 5ELI,
Sr: Generates L2. Also, the latch 3 in FIG.
, 5, 8.12 to 15.25 to 27 are each constituted by the same number of D-type flip-flops as the number of bits of the digital signal to be handled.

Next, the operation of the filter circuit shown in FIG. 1 will be explained.

The selector 2 in the first storage circuit 4 is connected to the control circuit 10
Due to the selector signal 5ELL from , the input signal SI is selected until the start point t1 of the slow and curve portion of the input signal Si, and the input signal S+ is output from the first storage circuit 4 as it is. Then, at the timing of the start point tl of the slope portion of the input signal S1, the selector 2 switches to a state in which the output signal of the latch 3 is selected.
The value of the input signal Si at 1 is stored in the latch 3, and from then on, this state is maintained and the stored value continues to be output until the timing of the end point t2 of the slope section. The value of the output signal Sj of the first storage circuit 4 during this period from t1 to t2 is equal to the value of the input signal S
This corresponds to the DC offset of L. Therefore, in the output signal 5k-S id -S j of the subtracter 6, D
C offset is removed.

On the other hand, the selector 7 in the second storage circuit 9 selects the output signal Sk of the subtracter 6 at least from the starting point tl to the ending point t2 of the slope portion of the input signal Si by the selector signal 5IEL2 from the control circuit 10. Since the signal Sk is output as is from the second storage circuit 9, the signal Sk from which the DC offset has been removed is input to the filter 11 as shown in L. Then, the input signal St
At the timing of the end point t2 of the slope section, the selector 7
By switching to a state in which the output signal Sm of the latch 8 is selected, the value of the output signal Sk of the subtracter 6 at t2 is stored in the latch 8, and this state is maintained for a predetermined period from the end point t2 of the slope section thereafter. and continues outputting the memorized value. As a result, the output signal 5I11 of the second storage circuit 9 maintains a constant value even after the end point t2 of the slope portion, so that ringing does not occur in the output of the filter 11 at the end point t2 of the slope portion. Note that during the period in which the selector 7 is in a state in which the latch 8 output signal S11 is selected by the select signal 5IEL2, that is, the second storage circuit 9 continues to output the value of the output signal Sk of the subtracter 6 at the slope section end point [2]. The time length of the period is selected to be long enough so that the influence of ringing after the slope portion of the output signal Sn of the filter 11 does not extend to the slope portion.

Although there is no ringing in the output signal Sn of the filter 11 as shown in FIG. 2, the DC offset that existed in the input signal Si is lost in the slope portion. Therefore, in the adder 24, the output signal Sj of the first storage circuit 4 which outputs the DC offset of the input signal S1 during the period t1 to t2 of the slope portion is added to the output signal Sn of the filter]1.
By adding , there is no ringing and DC
The output signal So after filtering with an offset is 1
4.

The present invention is not limited to the embodiments described above; for example, in the embodiment, a combination of a selector and a latch is used as the first and second memory circuits, but the latch operation (memory operation) and the input signal are A data latch that can selectively perform an output operation may also be used. A declutch having such a function is known as a transparent D latch. In addition, more simply, by using latches made up of D flip-flops 111 as the first and second storage circuits, and by normally supplying a relatively short-cycle clock to the latches made up of D flip-flops, it is possible to effectively input The signal may be output as is, and the clock may be stopped only when it is necessary to memorize it.

You may.

Furthermore, although the embodiment deals with an input signal in which a ramp signal exists intermittently, this is just an example, and the present invention is applicable to an input signal in which a valid signal exists intermittently. The present invention can be applied to all filter circuits that perform filter processing.

Further, the filter part is not limited to the configuration shown in FIG. 1, and the present invention is effective for any filter that causes ringing in the step response.

[Effects of the Invention] According to the present invention, the value of the starting point of the 9-effect signal in the input signal is stored and held in the first storage means, the DC offset of the input signal is detected, and this is subtracted from the input signal. By inputting it to the post-filter, the DC offset at the filter input end is removed, and by adding the DC offset output from the first storage means to the output of the filter again, the filter due to the DC offset is removed. It is possible to avoid ringing caused by step changes in the input. Furthermore, by storing and retaining the value of the end point of the a-effect signal in the input signal by the second storage means and inputting it to the filter, the effect of ringing at this end point appears within the period of existence of the a-effect signal. You can avoid it.

Therefore, in the filter circuit of the present invention, even if the input signal is only an intermittently present effective signal and includes a DC offset, the output signal includes steps at the start and end points of the effective signal of the input signal. Since ringing due to state changes does not occur, good filter processing is possible. Furthermore, when an averaging section is provided before the filter circuit, the averaging section only needs to be able to process the valid signal period of the input signal, so there is no need to increase the RAM size by 8. , peripheral recesses of RAM such as address counters are also simplified, and there are nine advantages in integrating circuits.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a filter circuit according to an embodiment of the present invention, Fig. 2 is a signal waveform diagram of each part to explain the operation of the filter circuit of Fig. 1, and Fig. 3 is a step response of the smoothing filter. FIG. 4 is a signal waveform diagram for explaining a problem when an input signal in which a ramp signal is intermittently present is processed by the smoothing filter of FIG. 1...Input terminal, 2.7...Selector, 3, 5, 8
゜12~15.25~27...Latch, 4...1st
6... Subtractor, 9... Second memory circuit, 10... Control circuit, 11... Filter, 16.1
7,21゜22...adder, 18-20...multiplier,
23...Divider, 24...Adder, 28...Output terminal. Applicant's agent Patent attorney Takehiko Suzue tl Figure 2 Figure

Claims (1)

[Claims] In a filter circuit that performs filter processing on an input signal in which a valid signal is present intermittently during a specific period, the value of the starting point of the valid signal of the input signal is stored and the stored value is used for at least the period of existence of the valid signal. a first storage means that outputs the input signal during the period and outputs the input signal as it is during the other period;
a subtraction means for subtracting the output signal of the first storage means from the input signal; and a subtraction means for storing the end point value of the effective signal in the output signal of the subtraction means and outputting the stored value for a predetermined period; a second storage means that outputs the output signal of the subtraction means as it is during the existence period of the valid signal; a filter that receives the output signal of the second storage means; 1. A filter circuit comprising: an adding means for adding the output signal of the first storage means.