JPH0246716A - Silicon wafer - Google Patents
Silicon waferInfo
- Publication number
- JPH0246716A JPH0246716A JP63197671A JP19767188A JPH0246716A JP H0246716 A JPH0246716 A JP H0246716A JP 63197671 A JP63197671 A JP 63197671A JP 19767188 A JP19767188 A JP 19767188A JP H0246716 A JPH0246716 A JP H0246716A
- Authority
- JP
- Japan
- Prior art keywords
- trench
- wafer
- orientation
- crystal
- flat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 15
- 229910052710 silicon Inorganic materials 0.000 title claims description 15
- 239000010703 silicon Substances 0.000 title claims description 15
- 239000013078 crystal Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 17
- 229910003460 diamond Inorganic materials 0.000 description 3
- 239000010432 diamond Substances 0.000 description 3
- 229910000976 Electrical steel Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/40—Crystalline structures
- H10D62/405—Orientations of crystalline planes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野１
本発明はシリコン・ウェーハのオリエンテーション フ
ラットの結晶方位に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to the crystal orientation of silicon wafer orientation flats.
［従来の技術］
従来（１００）結晶面から成るシリコン・つ工−ハのオ
リエンテーション フラットの結晶方位は（１１０＞で
あるのが通例であった。該従来シリコン・ウェーハのオ
リエンテーション フラットが（１１０）である理由は
、オリエンテーション フラットに垂直あるいは水平に
ダイヤモンド・スクライブを施す場合に、シリコン・ウ
ェーハの破断が行ない易いと云う理由からであった。[Prior art] Conventionally, the orientation flat of a silicon wafer consisting of a (100) crystal plane has generally had a crystal orientation of (110>).The orientation flat of a conventional silicon wafer has been (110). The reason for this is that silicon wafers are more likely to break when diamond scribing is performed vertically or horizontally on the orientation flat.
しかし、上記従来技術によるとシリコン・つ工−ハを用
いてトレンチ・ゲート ＭＯＳ ＦＥＴを製作する場
合に、トレンチの側壁に（１１０）結晶面が出てしまい
、該（１１０）結晶面のトレンチ・ゲート部は界面準位
密度が高くなり、ひいてはＭＯＳ ＦＥＴのトレンチ
・ゲートの側壁のみ、しきい値電圧が高くなってしまう
と云う課題があった。However, according to the above-mentioned conventional technology, when manufacturing a trench gate MOS FET using silicon, a (110) crystal plane appears on the side wall of the trench, and the trench with the (110) crystal plane There is a problem in that the interface state density becomes high in the gate portion, and as a result, the threshold voltage becomes high only on the sidewalls of the trench gate of the MOS FET.
本発明は、かかる従来技術の課題を解決し、シリコン・
ウェーハを用いてトレンチ・ゲート ＭＯＳ ＦＥＴ
を作成する場合に、トレンチ・ゲートの側壁にも（１０
０）結晶面が出る様に、シリコン・ウェーハのオリエン
テーション フラットを定める事を目的とする。The present invention solves the problems of the prior art and
Trench gate MOS FET using wafer
When creating a trench gate sidewall (10
0) The purpose is to determine the flat orientation of the silicon wafer so that the crystal plane is exposed.
［課題を解決するための手段］
上記課題を解決するために、本発明は、シリコン・ウェ
ーハに関し、（１００）結晶面を有するシリコン・ウェ
ーハのオリエンテーション フラットの結晶方位を＜１
００）となす手段をとる。[Means for Solving the Problems] In order to solve the above problems, the present invention relates to a silicon wafer, and provides a flat crystal orientation of a silicon wafer having a (100) crystal plane.
00).
〔実 施 例１
第１図は本発明の実施例を示すシリコン・ウェーハの平
面図であり、第２図は、本発明によるシリコン・ウェー
ハを用いてトレンチ部を形成した場合のトレンチ内結晶
面を示す断面図である。[Example 1] Figure 1 is a plan view of a silicon wafer showing an example of the present invention, and Figure 2 is a crystal plane in the trench when a trench portion is formed using the silicon wafer according to the present invention. FIG.
すなわち、第１図では、例えば厚さ４００μｍ厚で５″
φのＳｉウェーハ１の表面の結晶面を（１００）となし
、該Ｓｉウェーハ１に付ける数１０ｍｍ厚さのオリエン
テーション フラット２の結晶方位を＜１００＞となし
た状態を示したものである。That is, in FIG. 1, for example, the thickness is 400 μm and 5"
The crystal plane of the surface of the Si wafer 1 with a diameter of φ is set to (100), and the crystal orientation of the orientation flat 2 several tens of mm thick attached to the Si wafer 1 is set to <100>.
いま、このＳｉウェーハ１を用いて、トレンチ・ゲート
ＭＯＳ ＦＥＴを製作する場合に、ゲート・パター
ンは、オリエンテーション フラットに垂直及び水平に
描かれるために、本Ｓｉウェーハ１の表面からドライ
エツチングにより形成されるトレンチの断面は第２図の
如く、Ｓｉ基板１の表面から形成されたトレンチ部４の
トレンチ側壁５の結晶方位は（１００）となり、トレン
チ底面６の結晶方位も（１００）となる。Now, when fabricating a trench gate MOS FET using this Si wafer 1, the gate pattern is drawn vertically and horizontally in the orientation flat, so the dry pattern is removed from the surface of the Si wafer 1.
The cross section of the trench formed by etching is shown in FIG. 2, and the crystal orientation of the trench side wall 5 of the trench portion 4 formed from the surface of the Si substrate 1 is (100), and the crystal orientation of the trench bottom surface 6 is also (100). becomes.
尚、オリエンテーション フラットを（１００）にする
ことにより、ダイヤモンド スクライバ−による破断は
困難となるが、最近は、Ｓｉつ工−ハの切断は、ダイヤ
モンド ホイールと云う薄いダイヤモンド埋込みホイー
ルを高速で回転させて、Ｓｉウェーハを表面から裏面ま
で完全に切断するフル・カット・ダイシングが常用され
て居り、この問題は発生しない状況となっている。By setting the orientation flat to (100), it becomes difficult to break the steel with a diamond scriber, but recently, cutting of silicon steel is done by rotating a thin diamond-embedded wheel called a diamond wheel at high speed. Full-cut dicing, which completely cuts a Si wafer from the front surface to the back surface, is commonly used, and this problem does not occur.
本発明によりトレンチ・ゲート ＭＯＳ ＦＥＴのト
レンチ内側壁も（１００）結晶面化することができ、し
きい値電圧の増加を防止することができる効果がある。According to the present invention, the inner wall of the trench of a trench gate MOS FET can also be made into a (100) crystal plane, which has the effect of preventing an increase in threshold voltage.
第１図は本発明の実施例を示すシリコン・つニーへの平
面図であり、第２図は本発明によるシリコン・ウェーハ
を用いてトレンチ部を形成した場合のトレンチ部を示す
断面図である。
Ｓｉウェーハ
オリエンテーション
Ｓｉ基板
トレンチ部
トレンチ側壁
トレンチ底面
フラット
以上
第１図
出願人 セイコーエプソン株式会社
代理人 弁理士 上 柳 雅 誉（他１名）第２図FIG. 1 is a plan view of a silicon tunnel showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a trench portion formed using a silicon wafer according to the present invention. . Si wafer orientation Si substrate trench section trench sidewall trench bottom flat or better Figure 1 Applicant: Seiko Epson Corporation Agent Patent attorney Homare Kamiyanagi (1 other person) Figure 2
Claims (1)
ン・テーションフラットの結晶方位を（１００）となす
事を特徴とするシリコン・ウェーハ。Orientation of a silicon wafer having a (100) crystal plane A silicon wafer characterized in that the crystal orientation of the flat is (100).
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63197671A JPH0246716A (en) | 1988-08-08 | 1988-08-08 | Silicon wafer |
| EP19890114205 EP0354449A3 (en) | 1988-08-08 | 1989-08-01 | Semiconductor single crystal substrate |
| KR1019890011143A KR900003981A (en) | 1988-08-08 | 1989-08-04 | Semiconductor single crystal substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63197671A JPH0246716A (en) | 1988-08-08 | 1988-08-08 | Silicon wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0246716A true JPH0246716A (en) | 1990-02-16 |
Family
ID=16378398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63197671A Pending JPH0246716A (en) | 1988-08-08 | 1988-08-08 | Silicon wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0246716A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03262110A (en) * | 1990-03-13 | 1991-11-21 | Matsushita Electron Corp | solid-state imaging device |
| JP2003017698A (en) * | 2001-07-04 | 2003-01-17 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method therefor |
| JP2010062477A (en) * | 2008-09-05 | 2010-03-18 | Rohm Co Ltd | Trench type semiconductor device and its manufacturing method |
| JP2012227255A (en) * | 2011-04-18 | 2012-11-15 | Fuji Electric Co Ltd | Trench insulated gate type semiconductor device |
-
1988
- 1988-08-08 JP JP63197671A patent/JPH0246716A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03262110A (en) * | 1990-03-13 | 1991-11-21 | Matsushita Electron Corp | solid-state imaging device |
| JP2003017698A (en) * | 2001-07-04 | 2003-01-17 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method therefor |
| JP2010062477A (en) * | 2008-09-05 | 2010-03-18 | Rohm Co Ltd | Trench type semiconductor device and its manufacturing method |
| JP2012227255A (en) * | 2011-04-18 | 2012-11-15 | Fuji Electric Co Ltd | Trench insulated gate type semiconductor device |
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