JPH0246736A - Bipolar thin-film semiconductor device - Google Patents

Abstract

PURPOSE:To improve current driving ability and responsiveness, to enlarge effective emitter-base junction area and to increase current amplification factor hFE by providing a base lead-out region connected with a base electrode and having low dopant concentration on an insulating substrate, providing a thin-film semiconductor device thereon through an insulating layer and connecting substantially all of its base region with the base lead-out region. CONSTITUTION:A polycrystalline silicon layer, deposited on an insulating substrate 1, is highly doped with a P-type dopant and patterned into configurations as desired to provide a P<+>type base lead-out region 4b. A silicon oxide film 8 serving as an insulating film is provide on the region 4b. A polycrystalline silicon layer 2 as a semiconductor thin film is deposited all over the surface to provide an N<->type doped region, which is patterned into configurations as desired. Subsequently, a P-type doped region is formed and N<+>type emitter region 3 and an N<+>type collector region 5b are formed simultaneously. The P<+>type base lead-out region 4b is connected with the P-type base region 4a through a base connecting opening 8H.

Description

[Detailed description of the invention] A. Industrial application field The present invention relates to a bipolar thin film semiconductor device.

B. Prior Art A conventional bipolar thin film semiconductor device will be explained with reference to FIGS. 4 and 5. FIG. Figure 4 is patent application No. 62-14804.
A plan view of the bipolar thin film semiconductor device shown in No. 3,
FIG. 5 is a sectional view taken along the line v-v.

4 and 5, a polycrystalline silicon layer 22 as a semiconductor thin film is formed on an insulating substrate 21 using LPGV.
It is deposited to a desired thickness by a (low-pressure chemical vapor deposition) method and patterned into a desired shape.

This polycrystalline silicon layer 22 has an N0 type emitter region 23.
A P-type base region 24a and a P4-type base extraction region 24b surround this N"-type emitter region 23.
and an N+ type emitter region 23. N- so as to surround the P-type base area 24a and the P-type base drawer area 24b
A shaped collector region 25a is formed. The N-type impurity concentration in the N-type collector region 25a is lower than the P-type impurity concentration in the P-type base region 24a and the P''-type base extraction region 24b.

Further, an N-type collector lead-out region 25b doped with N-type impurities at a high concentration is formed so as to surround this N-type collector region 25a.

Here, the P-type base region 24a and the N1-type emitter region 23 are formed by using the same mask provided on the polycrystalline silicon layer 22 to form the P-type base region 24a and the N1-type emitter region 23 in the polycrystalline silicon layer 22 to which N-type impurities have been added at a low concentration in advance. It is formed by double diffusion of a type impurity and an N type impurity. Therefore, the width of the P-type base region 24a sandwiched between the N1-type emitter region 23 and the N-type collector region 25a is defined by the difference in lateral diffusion length due to double diffusion of P-type impurities and N-type impurities. , the base width W is extremely narrow.

Furthermore, a silicon oxide film 27 is deposited on the polycrystalline silicon layer 22 as an interlayer insulating film.

Through the contact holes opened in this silicon oxide film 27, the N+ type emitter region 23.degree.
B, and is connected to the collector electrode 26C.

This conventional bipolar thin film semiconductor device is manufactured as follows.

Polycrystalline silicon M22 as a semiconductor thin film is deposited on the insulating substrate 21 to a required thickness by the LPCVD method, and N
A required amount of type impurity is added to make the entire area a low concentration N-type impurity region, and patterned into a desired shape. A silicon oxide film as a mask material is then formed on the polycrystalline silicon layer 22 which has been made into an N-type impurity region, and a double diffusion window is opened at a predetermined position. Next, using the silicon oxide film having the double diffusion window as a mask, a required amount of P-type impurity is added to form a P-type impurity region for forming a base region and a base extraction region. Next, the part of the double diffusion window on the P-type impurity region for forming the base protruding region is covered with a silicon oxide film, and the silicon oxide film formed as a mask material on the polycrystalline silicon layer 22 is covered. A diffusion window is opened in the oxide film to form a collector extraction region.

Thereafter, using a silicon oxide film having a double diffusion window partially covered with a silicon oxide film and a diffusion window for forming a collector extraction region as a mask, a required amount of N-type impurity is added to form a high-concentration N+ A type emitter region 23 and a highly doped N" type collector lead-out region 25b are formed at the same time.

The P type impurity region sandwiched between the N" type emitter region 23 and the N- type impurity region thus formed becomes the P type base region 24a and the P+ type base lead-out region 24b, and the P type base region 24a and the P+ type base The N-type impurity region sandwiched between the lead-out region 24b and the N"-type collector lead-out region 25b becomes the N-type collector region 25a.

At this time, the base width W of the P type base region 24a sandwiched between the N+ type emitter region 23 and the N− type collector region 25a
is the P-type impurity forming the P-type base region 24a and N3
Since it is defined by the difference in lateral diffusion length due to double diffusion with the N-type impurity forming the emitter region 23, it is controlled to be extremely narrow.

Next, a silicon oxide film 27 is formed on the entire surface as an interlayer insulating film.
After depositing, contact holes are opened at predetermined positions on the N+ type emitter region 23, the P4 type base extraction region 24b, and the N+ type collector extraction region 25b, respectively, and the N3 type emitter region 23, the P゜ type base The emitter electrode 26E and the base electrode 2 are connected to the extraction region 24b and the N-shaped collector extraction region 25b, respectively.
6B and a collector electrode 26G are formed.

In this way, the bipolar type thin film semiconductor device shown in the above-mentioned Japanese Patent Application No. 148043/1980 has N in the semiconductor thin film.
''' type emitter region 23-P type base region 24a-N-
NP of horizontal N''-P-N- structure of collector region 25a
N bipolar transistors are formed. This P-type base region 24a is formed by doubly diffusing P-type impurities and N-type impurities through the same window opened in the mask material on the semiconductor thin film, and by diffusing the lateral diffusion lengths of these two types of impurities. The base width W of the P-type base region 24a is determined. So-called DSA (Diffusion 5elf)
Alignment) technology. Therefore, the base width W of the P-type base region 24a can be controlled to an extremely narrow (several thousand) desired base width, and even a material with a short diffusion length of minority carriers, such as the polycrystalline silicon layer 22, can be controlled to an appropriate width. An NPN bipolar transistor having a current amplification factor hFE can be made.

C0 Problems to be Solved by the Invention However, in such a conventional bipolar thin film semiconductor device, the width of the base region 24a is extremely narrow, so that the base resistance becomes extremely high, and as a result, the collector current cannot flow sufficiently. The response is poor. Also, if you try to make a sufficient amount of collector current flow, the drive voltage will increase. ■If you increase the impurity concentration in the base region to lower the base resistance, the emitter injection efficiency will decrease and the current amplification factor h
There were problems such as a decrease in Fε.

The present invention was made by focusing on these conventional problems, and improves current drive capability and responsiveness, increases the effective emitter-base junction area, and increases the current amplification factor hFE. An object of the present invention is to provide a bipolar thin film semiconductor device that can perform the following steps.

The present invention provides an emitter region of a second conductivity type formed in a semiconductor thin film, a collector region of a second conductivity type formed in a semiconductor thin film, and an emitter region sandwiched between the emitter region and the collector region. The base region and the emitter region are formed on a semiconductor thin film by double diffusion of impurities of the first conductivity type and the second conductivity type using a mask. It is applied to bipolar thin film semiconductor devices.

The above-mentioned problem is solved by forming a base lead-out region of the first conductivity type with a high impurity concentration on the substrate, and then forming an emitter on the base lead-out region via an insulating film.

By stacking the semiconductor thin films in which the collector and base regions are formed, and connecting almost the entire base region to the base lead-out region connected to the base electrode through an opening provided in the insulating film. resolved.

Since almost the entire area of the base region with the narrow E0 action width is connected to the base electrode via the base lead-out region of the first conductivity type with a high impurity concentration, the base resistance becomes low. Therefore, the current driving ability and responsiveness are significantly improved, and the effective emitter-base junction area is increased, so that the current amplification factor hFE can be increased.

F. Embodiment 1 First Embodiment A first embodiment of a bipolar thin film semiconductor device according to the present invention will be described with reference to FIGS. 1 and 2. FIG. FIG. 1 is a plan view showing a bipolar thin film semiconductor device, and FIG. 2 is a sectional view taken along line n-m.

1 and 2, a P1 type base lead region 4b is formed on an insulating substrate 1 by doping a polycrystalline silicon layer with P type impurities at a high concentration.

A polycrystalline silicon layer 2 as a semiconductor thin film is formed on this P-shaped base lead-out region 4b with a silicon oxide film 8 as an insulating film interposed therebetween.

In this polycrystalline silicon layer 2, there is an N1 type emitter region 3 doped with N type impurities, and this N3 type emitter region 3.
A P-type base region 4a surrounding the P-type base region 4a and an N-type collector region 5a surrounding the P-type base region 4a are formed. The N-type impurity concentration of this N-type collector region 5a is lower than the impurity concentration of P-type base region 4a. Furthermore, an N+ type collector extraction region 5b doped with N type impurities at a high concentration is formed surrounding this N− type collector region 5a.

In this way, the polycrystalline silicon layer 2 is coated with N1 type emitter region 3-P type base region 4a-N- type collector region 5a.
-Horizontal N''-P-N- of N+ type collector drawer area 5b
-N” structure is formed.

Note that the P type base region 4a and the N3 type emitter region 3
As will be described in detail later in the explanation of the manufacturing method, since it is formed by the so-called DSA technique in which P-type impurities and N-type impurities are doubly diffused into the polycrystalline silicon layer 2 using the same mask, The base width W of the P-type base region 4a sandwiched between the N"-type emitter region 3 and the N-type collector region 5a can be extremely narrow to several thousand angstroms. Furthermore, the P-type base region 4a can be an N""-type emitter region. It has a uniform base width W all around the 3.
The entire P-type base region 4a serves as an active base region that contributes to transistor operation.

The silicon oxide film 8 is provided with an opening 8H for base connection that includes the entire bottom surface of the P-type base region 4a and is slightly larger than the bottom surface of the P-type base region 4a. The drawer region 4b and the P-shaped base region 4a are connected.

Further, a silicon oxide film 7 as an interlayer insulating film is provided on the P0 type base lead-out region 4b and on the polycrystalline silicon layer 2.
is deposited. Through the contact holes opened in this silicon oxide film 7, the N-type emitter region 3, the P+-type base lead-out region 4b, and the N+-type collector lead-out region 5b are connected to an emitter electrode 6E made of, for example, aluminum AQ, and a base electrode, respectively. 6B and collector electrode 6C.

Next, a method for manufacturing such a bipolar thin film semiconductor device will be explained.

A polycrystalline silicon layer as a semiconductor thin film is deposited on the insulating substrate 1 to a required thickness by the LPCVD method, and boron B
Adding high concentrations of P-type impurities such as

Further, it is patterned into a desired shape to form a highly concentrated P+ type base extraction region 4b. A silicon oxide film 8 as an insulating film is formed on this P1 type base extension region 4b, and a base connection opening 8H is opened at a predetermined position where a base region is to be formed.

Next, a polycrystalline silicon layer 2 as a semiconductor thin film is applied to the entire surface.
is deposited to a required thickness by LPCVD, and a required amount of N-type impurities such as phosphorus P or arsenic As is added to form a low concentration N-type impurity region as a whole, and patterned into a desired shape. Then, a silicon oxide film as a mask material is formed on the polycrystalline silicon layer 2 as the N-type impurity region, and a window for double diffusion is opened at a predetermined position.

Next, using the silicon oxide film having the double diffusion window as a mask, a required amount of P-type impurity such as boron B is added to form a P-type impurity region. Then, a window for forming a collector lead-out region is opened again at a predetermined position of the silicon oxide film having the double diffusion window. Using this silicon oxide film having the double diffusion window and the collector lead-out region forming window as a mask, a required amount of N-type impurities such as IJ-P and arsenic As are added to form the high-concentration N1-type emitter region 3 and the N-type A collector draw-out region 5b is formed at the same time.

The P type impurity region sandwiched between the N+ type emitter region 3 and the N− type impurity region thus formed is the P type base region 4.
a, and the N- type impurity region sandwiched between the P-type base region 4a and the N+-type collector lead-out region 5b becomes the N- type collector region 5a.

P-type impurities and N-type impurities are double-diffused from the same double-diffusion window to form a P-type base region 4a and an N-type emitter region 3.
In order to form a This will be the base area. Moreover, this P-type base region 4a is formed by using the so-called DSA technique in which the base width W is determined by the difference in lateral diffusion length of two types of impurities by the above-mentioned double diffusion method. The width W is controlled to an extremely narrow desired base width of several thousand angstroms.

On the other hand, the base connection opening 8H opened in the silicon oxide film 8 includes the entire bottom surface of the P-type base region 4a and is slightly larger than the bottom surface of the P-type base region 4a. The P-shaped base drawer region 4b and the P-shaped base region 4a are connected.

Next, after depositing a silicon oxide film 7 as an interlayer insulating film on the entire surface, a silicon oxide film 7 is deposited as an interlayer insulating film on the N″″ type emitter region 3, on the P4 type base extraction region 4b, and on the N+ type collector extraction region 5.
Contact holes are respectively opened at predetermined positions on b. Then, an aluminum AQ layer is formed on the entire surface and patterned into a predetermined shape to form an N3 type emitter region 3, P0
An emitter electrode 6E, a base electrode 6B, and a collector electrode 6C are formed, which are connected to the N+ type base extraction region 4b and the N+ type collector extraction region 5b, respectively.

In this way, in the first embodiment, the entire bottom surface of the P type base region 4a, which has an extremely narrow base width W, is connected to the highly concentrated P+ type base extraction region 4b, so that the base resistance can be made extremely small. be able to. Therefore, current drive ability and responsiveness are significantly improved.

Here, the P4 type base lead-out region 4b is not only connected to the P type base region 4a, but also connected to a part of the N-type emitter region 3 adjacent to the P-type base region 4a and the N-
It is also connected to the shaped collector region 5a. However, P″
The P-N junction formed between the "" type base drawer area 4b and the N1 type emitter area 3 is the P9 type base drawer area 4b.
Since the impurity concentration in the P-type base region 4a is considerably higher than that in the P-type base region 4a, the injection of minority carriers is suppressed.
There is no adverse effect on transistor operation. Also,
P0 type base drawer area 4b and N-type collector area 5a
Since a reverse bias is applied to the P-N junction formed between the transistor and the transistor during operation, it does not pose a problem unless the power supply voltage is increased considerably.

Further, the P-type base region 4a around the N''''-type emitter region 3 has a uniform base MW over the entire region, and this P-type base region 4a has a uniform base MW over the entire region.
Since the entire shaped base region 4a becomes an active base region contributing to transistor operation, the effective emitter-base junction area can be increased.

Furthermore, similarly to the bipolar thin film semiconductor device shown in Japanese Patent Application No. 62-148043, the base width W of the P-type base region 4a can be reduced to an extremely narrow desired base width by the double diffusion method using the same mask. Since the current amplification factor hFE can be controlled, the current amplification factor hFE can be increased, and since the low concentration N-type collector region 5a is provided, the withstand voltage can be increased.

Second Embodiment Next, a second embodiment of the bipolar thin film semiconductor device according to the present invention will be described with reference to FIG.

In FIG. 3, which is a sectional view of a bipolar thin film semiconductor device, an N-type semiconductor substrate 31 is used in place of the insulating substrate 1 in the first embodiment shown in FIG. Moreover, instead of the P0 type base extraction region 4b, a P" type base extraction region 34b as a high concentration P+ type impurity region formed by adding P type impurity at a high concentration to the surface of the N type semiconductor substrate 31 is provided. Furthermore, instead of the silicon oxide film 8, a silicon oxide film 38 is used as an insulating film formed on the P+ type base lead-out region 34b.

Other than these, it is the same as shown in Figure 2,
A silicon oxide film 38 is formed on the P3 type base extraction region 34b.
A polycrystalline silicon layer 2 is formed through the polycrystalline silicon layer 2, and this polycrystalline silicon layer 2 has an N0 type emitter region 3, a P type base region 4a, an N-type collector region 5a, and the like as described above.
Horizontal shape of N”-shaped collector drawer area 5b: N”-P-N-N
+ Structure is formed. Further, the silicon oxide film 38 is provided with a base connection opening 38H that includes the entire bottom surface of the P-type base region 4a and is slightly larger than the bottom surface of the P-type base region 4a.
The P2 type base drawer area 34b and the P type base area 4a are connected via this base connection opening 38H.

That is, the second embodiment can be used in a semiconductor device having a structure in which the P type base region 4a is not insulated from the N type semiconductor substrate 31.

Note that since the P-type base region 4a and the N""-type emitter region 3 are formed by double diffusion similar to the first embodiment, the base width W of the P-type base region 4a is It has an extremely narrow base width W of several thousand angstroms, and has a uniform base width W all around the N''' emitter region. However, the entire P-shaped base drawer 4a serves as an active base region.

In this manner, in the second embodiment as well, the entire bottom surface of the P-type base region 4a is covered with high concentration P.
Since it is connected to the type 3 base drawer area 34b, it has exactly the same effect as the first embodiment.

In addition, in the above first and second embodiments, NPN
I have talked about bipolar transistors, but this N
The present invention can also be applied in exactly the same way to a transistor having a structure in which the conductivity types of P-type and P-type are interchanged throughout, that is, a PNP bipolar transistor. Further, the layout of the bipolar transistor formed in the polycrystalline silicon layer 2 is not limited to the embodiment without departing from the present invention.

G6 Effects of the Invention As described above, according to the present invention, in a bipolar thin film semiconductor device formed in a thin film semiconductor layer, a base extraction region with a high impurity concentration connected to a base electrode is provided on an insulating substrate. A thin film semiconductor device is formed on top with an insulating layer interposed therebetween, and almost the entire base region is connected to the base lead-out region. ■The base resistance can be made extremely small, significantly improving current drive ability and responsiveness. The following effects can be obtained: (1) the effective emitter-base junction area can be increased; and (2) the current amplification factor hFE can be increased.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a bipolar type thin film semiconductor device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line nn, and FIG. 4 is a plan view showing a conventional bipolar type thin film semiconductor device, and FIG. 5 is a sectional view taken along the line v--v of the thin-film semiconductor device. 1: Insulating substrate 2: Polycrystalline silicon layer 3: N4 type emitter region 4a: P type base extraction region 4b: P'' type base extraction region 5a: N- type collector region 5b: N'' type collector extraction region 6E: Emitter electrode 6B: Base electrode 6C: Collector electrode 7: Silicon oxide film 8: Silicon oxide film 8H: Opening 3: N-type semiconductor substrate 34b: P+ type base extraction region Patent applicant: Nissan Motor Co., Ltd. Representative Patent Attorney Fuyuki Nagai Figure 3

Claims (1)

[Scope of Claims] An emitter region of a second conductivity type formed in a semiconductor thin film, a collector region of a second conductivity type formed in the semiconductor thin film, and a second conductivity type emitter region sandwiched between the emitter region and the collector region. 1
a base region of a conductivity type, the base region and the emitter region being formed by double diffusion of impurities of a first conductivity type and a second conductivity type using the same mask provided on the semiconductor thin film. In a bipolar thin film semiconductor device, a base lead-out region of a first conductivity type with a high impurity concentration is formed on a substrate, and each of the emitter, collector, and base regions is formed on the base lead-out region with an insulating film interposed therebetween. The bipolar type is characterized in that the semiconductor thin films are stacked, and substantially the entire area of the base region is connected to the base lead-out region connected to the base electrode through an opening provided in the insulating film. Thin film semiconductor device.