JPH0246737A - Manufacture of iii-v compound semiconductor element - Google Patents

Abstract

PURPOSE:To prevent expansion of an active layer of a P-channel FET by forming a semiconductor layer doped with group IV atoms on a substrate, ion implanting group III or V atoms into a required region of the semiconductor layer, subjecting it to heat treatment for reversing the conductivity of the ion- implanted region, providing Schottky electrodes on the regions having a different conductivity and providing ohmic electrodes on the opposite sides of each Schottky electrode. CONSTITUTION:Si ions are implanted into a semi-insulating GaAs substrate 121 masked with a photoresist 122a. Subsequently, Ga ions are implanted into a region where a P-channel FET is to be produced, masked with a photoresist 122b. A high-melting-point metal is deposited on the surface of the substrate 121 and subjected to reactive ion etching to provide Schottky electrodes 125 for the gate. Si ions are implanted by using a photoresist 122c as a mask. Further, Ga ions are implanted by using a photoresist 122d and the gate electrodes 125 as a mask. After the resist 122d is removed, all the surface is coated with SiN and heat treatment is performed. Finally, ohmic electrodes 132 are vapor deposited on the opposite sides of the Schottky electrode 125 and heat treatment is performed for alloying the same.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a ■-v group compound semiconductor device,
In particular, it relates to a method of manufacturing complementary field effect transistors.

[Prior art] ■-V group compound semiconductor materials, including GaAS,
It has a feature of higher electron mobility than conventional Si, and it is of great significance to use this material to construct ultra-high-speed integrated circuits. When constructing such an ultra-high-speed integrated circuit, GaAs requires an M E as shown in Fig. 3(a).
S F E T (Metal Sem1conduc
torField Effect Transisto
r) is used for the tail.

This MESFET has a conductive semiconductor layer 2 formed on a semi-insulating substrate 1, on which a Schottky electrode 3 serving as a gate, and two ohmic electrodes 4 serving as a source and a drain placed on both sides of the Schottky electrode 3. It has a structure. In addition, in order to reduce the eccentric resistance of the element, as shown in Figure 3(b),
It is also widely practiced to use a structure having semiconductor layers 1fi, 5 into which impurities are introduced at a high concentration under two ohmic electrodes.

By the way, when configuring a large-scale integrated circuit using the above-mentioned MESFET, an FET (
n-channel FET) and FET with p-type layer as channel
It is advantageous to use a complementary circuit combining (n-channel FET) to reduce power consumption. FIG. 4 is a diagram showing an inverter using a complementary circuit, in which the gates of two FETs, n-channel FET 13 and n-channel FET 14, are connected to the input terminal 15, the drains are connected to the output terminal 16, and the sources of the n-channel FETs are connected to the ground terminal 17. , n-channel FET
The source of the circuit is connected to the power supply terminal 18.

When configuring a complementary circuit using the MESFET, an FET whose active layer is a region into which n-type impurities and p-type impurities are ion-implanted as described below is used.
This is possible by manufacturing. Figures 5(a) to (f)
) is a cross-sectional view of a substrate showing this manufacturing method in the order of steps.

An n-type impurity such as Si is ion-implanted into a semi-insulating GaAs substrate 521 using a photoresist 522a with openings in only desired regions as a mask to form an active layer 528 of an n-channel FET (FIG. 5(a)).

A p-type impurity such as Hp is ion-implanted using a photoresist 522b with openings in different regions as a mask to form an active layer 537 of an n-channel FET (FIG. 5(b)).

Subsequently, a high melting point metal such as WSi is deposited on the surface of the substrate 521 and processed by reactive ion etching to form a gate Schottky electrode 525 (FIG. 5(C)).

Using a photoresist 522C with an opening in the gate electrode 5256 and r) channel FET region as a mask, ions of r) type impurity such as Si are implanted to form a high temperature n type region 526 (FIG. 5(d)). .

Further, using the photoresist 522d with openings in the gate electrode 525 and the n-channel FET region as a mask, p-type impurities such as Hg are ion-implanted to form a high-temperature n-type region 538 (FIG. 5(e)). Next, the entire surface is covered with a protective film such as SiN, and heat treatment is performed to activate the ion-implanted impurities. Finally, ohmic electrodes 532 are deposited on both sides of the Schottky electrode 525, and an alloying heat treatment is performed to complete the device (FIG. 5(f)). Complementary MESFET circuits can be manufactured by such a manufacturing method.

[Problems to be Solved by the Invention] However, in the above method, the p-type impurities such as H(], 8e which are usually ion-implanted have a large diffusion rate and spread inside the substrate during heat treatment, so that the active layer is not placed on the substrate side. There was a problem in that it spread and deteriorate the characteristics of manufactured devices.

The present invention solves these conventional problems, suppresses the spread of the active layer of an n-channel FET, and provides a ■-v group compound semiconductor in which an n-channel using the above-mentioned FET and an n-channel FET are formed on the same substrate. The object of the present invention is to provide a method for manufacturing an element.

[Means for Solving the Problems] The present invention includes a step of forming a semiconductor layer on a substrate into which group IV atoms are introduced as impurities, and ion implantation of group (III) atoms or group V atoms into desired regions of the semiconductor layer. a step of inverting the conductivity type of the ion-implanted region by performing heat treatment; and a step of forming a Schottky electrode on the surface of each region having a different conductivity type and an ohmic electrode on both sides of the Schottky electrode. A method for manufacturing a group IV compound semiconductor device, characterized in that:

[Function] (1) The present invention will be described in detail below in the case where GaAs is used as the group V compound semiconductor layer, Si is used as the group IV impurity atom, and Ga is used as the ion-implanted element.

Figure 6 shows Si at 5 x 1012 cm at 120 keV.
This figure shows the dependence of the sheet carrier concentration and mobility on the dose of Ga ions after Ga ions were implanted at 340 keV into GaAs ion-implanted at −2 and 5×1011013C and heat-treated. Proceedings of the Academic Conference of the Japan Society for Applied Physics, page 848, lecture number 19p-7D-5). In the figure, ○ and Δ represent the ion implantation of Sl, mtfi 5 x 1012 cm-2, respectively.
;a Yo(j 5 x 1013cm-2(7)), where A is the sheet carrier concentration and B is the mobility.As can be seen from the figure, when the Ga dose is 1
At x 1011014C or higher, inversion of Si-doped GaAs from n-type (solid line in the figure) to p-type (broken line in the figure) is observed.

The present invention takes advantage of this phenomenon. Taking the above case as an example, after ion-implanting Ga into the S1-doped n-type GaAs channel layer in the region where the n-channel FET is to be formed,
By performing the heat treatment, only the Si-doped n-type GaAs layer in the Ga ion-implanted region is inverted to p-type, making it possible to manufacture n-channel and n-channel FETs on the same substrate. At this time, the p-type impurity is the conventional p-type impurity.
Since Si has a smaller diffusion than a type impurity, the active layer has less spread, and a high-performance n-channel FET can be manufactured.

[Example] Hereinafter, an example of the present invention will be described in which the ■-V group compound semiconductor is GaAs and the IV group impurity element is Si.

FIGS. 1(a) to 1(e) are cross-sectional views of a substrate showing the manufacturing method of the first embodiment of the present invention in the order of steps. Photoresist 1 with an n-channel FET and a region where the n-channel FET will be formed opened in a semi-insulating GaAs substrate 121
Using 22a as a mask, Si ions were implanted, and S1 implanted GaA
An s-layer 123 is formed (FIG. 1(a)).

Next, Ga ions are implanted into the region where the n-channel FET is to be manufactured using the photoresist 122b as a mask.
A Si-implanted GaAs layer 124 is formed (FIG. 1(b)).
).

Subsequently, a high melting point metal such as WSi is deposited on the surface of the substrate 121 and processed by reactive ion etching to form a Schottky electrode 125 of the gate (FIG. 1(C)).

This gate electrode 125 and the n-channel FET and n
Si ions are implanted using the photoresist 122C with an opening in the region where the channel FET is to be made as a mask, and high concentration Si is implanted.
An implanted GaA3 layer 126 is formed (FIG. 1(d)).

Ga ions are implanted using the photoresist 122d and the gate electrode 125, which are roughly opened in the region where the n-channel FET is to be fabricated, as masks, and high concentration Ga and Si are implanted into GaAs.
A layer 127 is formed (FIG. 1(e)).

Next, after removing the resist 122d, the entire surface is covered with SiN and heat treatment is performed to activate the ion-implanted impurities. By this heat treatment, the area 14.12 where only Si was implanted
3,126 exhibits n-type conductivity, and includes a ``1-type GaAs layer 123'' serving as an active layer and a high concentration n-type layer 123 for reducing parasitic resistance.
Form layer 1i! 1c126 is formed. Also, Si and Ga
The implanted regions 124 and 127 exhibit p-type conductivity,
A p-type GaAs layer 124 serving as an active layer and a high concentration p shadow region 127 are formed. Finally, the Schottky electrode 125
Ohmic electrodes 132 are deposited on both sides of the wafer and an alloying heat treatment is performed to complete the device (FIG. 1(f)).

Through the above steps, it has become possible to manufacture a complementary MESFET circuit while suppressing the spread of the active layer of the n-channel FET.

FIGS. 2(a) to 2(()) are substrate cross-sectional views showing the manufacturing method of the second embodiment of the present invention in the order of steps. First, a non-doped GaAs buffer is formed on a semi-insulating GaAs substrate 221 by molecular beam epitaxy. A layer 233 and a Si-doped n-type GaAS layer 234 are grown in this order (FIG. 2(a)).

Next, in order to electrically isolate adjacent FETs, oxygen ions are implanted into the region between each FET using the photoresist 222a as a mask, and the oxygen-implanted GaAs1, which is a semi-insulating region, is
i 235 (FIG. 2(b)).

Using a photoresist 222b with rough openings in the region where the n-channel FET is to be formed as a mask, Ga is ion-implanted.
Form a-implanted Si-doped GaA'J 236 (second
Figure (C)).

Next, after removing the resist 222b, a high melting point metal such as 13i is deposited on the surface and processed by reactive ion etching to form the Schottky electrode 225 of the gate (second
Figure (d)).

This gate electrode 225 and the n-channel FET and n
S: is ion-implanted using the photoresist 222C with an opening in the region where the channel FET is to be made as a mask, and high-concentration Si is
An implanted GaAs layer 226 is formed (FIG. 2(e)).

Ga ions are implanted using the photoresist 222d and the gate electrode 225, which are roughly opened in the region where the n-channel FET is to be fabricated, as masks, and high concentration Ga and Si are implanted into GaAs.
1l 227 is formed (FIG. 1(f)).

Next, after removing the resist 222d, the entire surface is covered with SiN and heat treatment is performed to activate the ion-implanted impurities. By this heat treatment, the region 226 into which only Si is implanted exhibits n-type conductivity, and a highly doped n-type layer 226 for reducing the parasitic resistance is formed. Also Ga.

The region 1234 where rM elements are not ion-implanted is "
) type conductivity is maintained and serves as a dynamic home for the n-channel FET. Roughly speaking, a region 236 in which Ga is ion-implanted into Si-doped GaAs@234 and a region 227 in which Sl and Ga are implanted exhibit p-type conductivity, and the p-type Ga that becomes the active layer
An As layer 236 and a high concentration p shadow region 227 are formed. Finally, ohmic electrodes 232 are deposited on both sides of the Schottky electrode 225, and heat treatment for alloying is performed to complete the device (FIG. 2(g)).

Through the above steps, it has become possible to manufacture a complementary MESFET circuit while suppressing the expansion of the active layer of the p-channel FET. In general, since the device manufactured according to this example can form a highly concentrated thin film active layer by molecular beam epitaxy, it is possible to shorten the gate while suppressing the short channel effect and manufacture a high-performance complementary MESFET integrated circuit. .

[Effects of the Invention] As explained above, according to the present invention, a complementary MESFET integrated circuit can be manufactured while suppressing the diffusion of ρ-type impurities, and an ultra-high-speed integrated circuit with low power consumption using this complementary MESFET can be produced. became possible.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views of a substrate showing an embodiment of the present invention in the order of steps, FIG. 3 is a cross-sectional view of a substrate showing the structure of a MESFET, and FIG. 4 is a circuit showing an inverter using complementary FETs. 5 is a cross-sectional view of a substrate showing the conventional manufacturing method in the order of steps, and FIG. 6 is a diagram showing the relationship between carrier areal density and mobility when Ga is ion-implanted into GaAs into which Si is ion-implanted. I'll go. 1... Semi-insulating substrate 2... Conductive semiconductor layer 3, 125,225.525... Schottky electrode 4, 132.232.532... Ohmic electrode 5
...Highly doped semiconductor region 3...") Channel FET 4...P channel FET 5...Input terminal 6...Output terminal 7...Ground terminal 8...Power terminal 121.221 , 521-...Semi-insulating GaAs substrate 1
22a-d, 222a-d, 522a-d ・7
t fillet cyst 123.528 ・Si-implanted GaAS layer 124 ・aa, s* implanted GaASlii 126.2
26,526--High concentration Si-implanted GaAs layer 127.
227...High concentration Ga, Si implanted GaAs112
33...Non-doped GaAs layer 234-3i Doped GaAS layer 235...Oxygen-implanted GaA3 layer 236-ea-implanted Si-doped GaAs 11537 ・M
(]Implanted GaAS layer 538...high concentration M (I-implanted GaAS layer Fig. 3)

Claims (1)

[Claims] (1) forming a semiconductor layer on a substrate into which group IV atoms are introduced as impurities, ion-implanting group III atoms or group V atoms into a desired region of the semiconductor layer and performing heat treatment;
The method is characterized by comprising the steps of inverting the conductivity type of the ion-implanted region, and forming a Schottky electrode on the surface of each region having a different conductivity type and an ohmic electrode on both sides of the Schottky electrode. A method for manufacturing a III-V group compound semiconductor device.