JPH0246747A - Formation of multilayer interconnection - Google Patents

Abstract

PURPOSE:To enable a silicon oxide film formed over a first interconnection layer to be coated with another silicon oxide film while preventing debonding from each other due to stress between these silicon oxide films or the like by forming a second silicon nitride film on a first silicon nitride film which has been flattened on the silicon oxide film formed over the first interconnection layer. CONSTITUTION:A first silicon nitride film 15 is formed on a silicon oxide film 17 which has been formed over a first interconnection layer 11 to have difference in level on the surface thereof. Further, a flattening film (e.g., resist) is formed thereon. The flattening film and the first silicon nitride film 15 are etched back to flatten the first silicon nitride film 15. The flattened first silicon nitride film 15 is covered with a second silicon nitride film 23, and a second interconnection layer 13 is formed over the second silicon nitride film 23.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for forming a multilayer wiring, in which a glabellar film on a first wiring layer is flattened, and then a second wiring layer is formed on the glabellar film. It is related to.

[Summary of the invention]

The present invention provides a method for forming a multilayer wiring as described above, in which a first silicon nitride film is formed on a silicon oxide film formed on the upper layer of the lth wiring layer, and the first silicon nitride film is planarized. By forming a second silicon nitride film on the nitride layer, even if another silicon oxide film is formed on the silicon nitride film to form a second wiring layer, stress between the silicon oxide films can cause stress between the two silicon oxide films. This is to prevent peeling etc.

[Conventional technology]

FIG. 2 shows a semiconductor device having a multilayer wiring structure having an IN polycrystalline Si wiring 11 and two layers of A1 wiring 12 and 13. In this multilayer wiring structure, a PSG film 14 is formed as a glabellar film between the Al wirings 12 and 13.

By the way, if the PSG IIl 14 is formed directly on the Al interconnect 12, a step will also occur in the PSG film 14 due to the step due to the Al interconnect 12, the polycrystalline St interconnect 11, etc. As a result, the coverage of the AI wiring *13 was not good, and the Al wiring 13
Lithography during processing is also not easy.

In order to solve these problems, a plasma SiN film 15 is formed on the Al wiring 12, and then a resist (not shown) or the like is applied and fired, and then this resist and plasma SiN film 15 are formed on the Al wiring 12.
Both are etched back under conditions such that the etching rate is equal to that of the N film 15, and plasma SiN is etched back as shown in FIG.
After the surface of the film 15 is flattened, the PSG film 14 is formed on the plasma SiN film 15.

That is, in the multilayer wiring structure shown in FIG. 2, both the PSG film 14 and the plasma SiN film 15 serve as interlayer films between the Al wirings 12 and 13.

[Problem to be solved by the invention]

By the way, in order to make the contact hole 16 shallow,
The thinner the glabella, the better. For this reason, the above-mentioned etchback is performed so as to leave as little of the plasma SiN film 15 for planarization as possible.

As a result, the As5G film 17, which is an interlayer film between the polycrystalline Si wiring I41All and the Al wiring 12,
1, or the plasma SiN film 15 becomes extremely thin at this portion.

In a portion where the plasma SiN film 15 has a thickness of about 50° or less, the PSG film 14 peels off or floats due to the heat treatment at 400 to 450° C. in the final Al sintering step.

[Means to solve the problem]

The method for forming a multilayer wiring according to the present invention includes a first wiring N11
A step of forming a first silicon nitride film 15 on the silicon oxide film 17 formed as an upper layer and having a stepped portion, and a step of forming a flattening film (for example, resist) on the first silicon nitride film 15. and etching back the planarization film and the first silicon nitride film 15 to form the first silicon nitride film.
a step of planarizing the silicon nitride film 15, a step of forming a second silicon nitride film 23 on the planarized first silicon nitride film 15, and a step of planarizing the second silicon nitride film 15.
I! 23, respectively.

[For production]

In the method for forming multilayer wiring according to the present invention, the first flattened
A second silicon nitride film 2 is further formed on the silicon nitride film 15.
3, even if the first silicon nitride film 15 disappears or becomes too thin at the top of the stepped portion of the silicon oxide film 17 during planarization of the first silicon nitride film 15, the silicon nitride film 15 at the top will not be removed. The thickness of the membrane 15.23 can be greater than a predetermined value.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In this example, a polycrystalline Si wiring 11 with a thickness of 0.4 μm is formed so as to extend on the field oxide film 22 of the St substrate 21, and this polycrystalline Si wiring 11 is
Cover with 5G film 17.

Next, the Al wiring 12 with a thickness of 0.4 pm is attached to the As5G film 17.
A plasma SiN film 15 with a thickness of 8,000 mm formed at a temperature of 250 to 350° C.
Cover 2. At this point, the surface of the plasma SiN film 15 is not flat due to the step difference caused by the Al wiring 12, the polycrystalline St wiring 11, and the like.

Next, a resist (not shown) is placed on the plasma SiN film 15.
After applying the resist to a thickness of 3,500 mm and baking the resist, the resist and the plasma SiN film 15 are etched back under conditions such that the etching rates of the plasma SiN film 15 are equal to each other.

This etchback is performed over a thickness of 1 μm, and the end point of the etchback is detected by time control. after that,
If the resist remaining in the valleys of the plasma SiN film 15 is removed, the surface of the plasma SiN film 15 becomes nearly flat as shown in FIG.

Note that the plasma SiN film 15 has no etching effect even after etching.
Since 2 is not released, it is easy to etch back together with a resist, and is suitable for planarization.

Next, in this example, the planarized plasma SiN film 1
5, plasma SiN is applied again at a temperature of 250 to 350°C.
The film 23 is formed to a thickness of 1000 mm.

Therefore, even if the As5G film 17 is exposed on the polycrystalline Si wiring 11 or the plasma SiN film 15 becomes extremely thin in this part due to the above-mentioned etchback, the plasma SiN film 15.23 in this part The thickness can be made greater than a predetermined value.

Next, by atmospheric pressure CVD at a temperature of 400°C, a thickness of 60°C was obtained.
A PSG film 14 of 0.000 nm is formed on the plasma SiN film 23, and a contact hole 16 is further formed. And A
I! Wiring 13 and PSG film 24 with a thickness of 7000A and a thickness of 3
000 plasma SiN films 25 are sequentially formed.

In this example, 400 to 450 in the A1 sintering step.
Even when heat treatment was performed at .degree. C., the PSG film 14 did not peel off or rise. This is because the plasma SiN film 15.23 has a thickness greater than a predetermined value even on the polycrystalline St wiring 11, so that the thickness of the ^SSG film 17 and PSGll1
It is thought that this is because the stress between the plasma SiN films 15 and 14 is balanced by the plasma SiN films 15 and 23.

In the above embodiments, the plasma SiN film 15 was used to form the PSG film 14 flatly, but instead of the plasma SiN film 15, a multilayer film such as a plasma SiN film/PSG film/plasma SiN film may be used. You can also do that.

〔Effect of the invention〕

In the method for forming a multilayer interconnection according to the present invention, the thickness of the silicon nitride film at the top of the stepped portion of the silicon oxide film can be made greater than a predetermined value. Even if another silicon oxide film is formed thereon, separation of the two silicon oxide films due to stress or the like will not occur.

[Brief explanation of the drawing]

FIGS. 1 and 2 are side sectional views of semiconductor devices having multilayer wiring formed according to an embodiment of the present invention and a conventional example, respectively. In addition, in the symbols used in the drawings, 11--
−・−・−−−−−・−・−−−−−A l wiring 15.
23--1--・--1-Plasma SiN film 17・-
・−・−・−・−−−−−−AsSG film.

Claims (1)

[Scope of Claims] A step of forming a first silicon nitride film on a silicon oxide film formed on a first wiring layer and having a stepped portion, and on the first silicon nitride film. forming a planarizing film on the planarized silicon nitride film; etching back the planarizing film and the first silicon nitride film to planarize the first silicon nitride film; A method for forming a multilayer wiring, comprising the steps of: forming a second silicon nitride film on a silicon nitride film; and forming a second wiring layer over the second silicon nitride film.