JPH0247034B2 - - Google Patents

Description

[Detailed Description of the Invention] (Technical Field) This invention relates to a MOS suitable for use in a dynamic random access memory (hereinafter referred to as D-RAM).
The present invention relates to a type word line signal driving circuit.

(Conventional technology) MOS with large storage capacity and fast access time
In order to realize a highly integrated type D-RAM, it is necessary to reduce the size of the MOS transistors that are its constituent elements. As a result, the gate length becomes short, and leakage current between the drain and source may increase due to the so-called short channel effect. Therefore, the word line signal drive circuit in the D-RAM may malfunction due to this leakage current. That is, after switching to page mode and selecting a word line and applying an activation signal to set it to a high level (hereinafter referred to as "H"), bit lines are sequentially selected and data is written into the memory cell. In the process, the "H" potential of the selected word line may drop due to the aforementioned leakage current, resulting in a situation in which writing cannot be performed completely. D-
When designing a RAM, the gate length is shortened to the extent that the short channel effect mentioned above does not occur, but the short channel effect does not occur.
Because it depends largely on the magnitude of the voltage applied between the drain and source of the MOS transistor, the memory cell section, where the applied voltage is relatively low, and the peripheral circuit section, such as the word line signal drive circuit, where the applied voltage is relatively high, have the same specifications. When transistors are designed in this way, the above-mentioned problems often occur.

(Purpose) The purpose of this invention is to eliminate the occurrence of malfunctions due to the short channel effect while satisfying the short channel requirements for high speed.
The present invention provides a MOS type word line signal driving circuit.

(Summary) In order to achieve the above object, the present invention is such that the threshold voltage of some MOS transistors in the word line signal drive circuit is made larger than that of other transistors. This will be explained in detail based on the following.

(Embodiment) FIG. 1 is a circuit connection diagram of a D-RAM to which the present invention is applied, including a word line signal drive circuit.

The word line signal drive circuit has one end connected to the word line activation signal terminal P, and operates the word line in response to word line selection signals D ₁ , D ₂ . . . Dn supplied to the gates.
Transistors Q ₁₁ , Q ₁₂ , ... Q _1o that transmit activation signals to L ₁ , L ₂ ...Ln, and the word lines L ₁ , L ₂ ...Ln
Reset circuit 10 for resetting the above activation signal
It consists of Reference numeral 20 denotes a memory section in which memory cells each consisting of a combination of a transistor T and a capacitor C are arranged in a matrix. Each memory cell has word lines L ₁ , L ₂ ...Ln and bit lines B ₁ , B ₂ , ...Bn
The storage is performed by selectively storing charge in the capacitor C.

In conventional circuits, the gate lengths of all transistors including the transistor T constituting the memory were designed to be the same, but in the circuit shown in Figure 1, the transistors surrounded by dotted lines in the figure
The threshold voltages of Q ₁₁ , Q ₁₂ , Q _1o , Q ₂₁ , Q ₂₂ . . . Q _2o are set higher than those of other transistors. In order to increase the threshold voltage of some transistors without increasing the manufacturing process, it is sufficient to make the gate length longer than that of other transistors, and this can be easily done by simply changing some of the photolithography masks. It can be realized.

Next, the operation of the circuit shown in FIG. 1 will be described. For simplicity, the explanation will be limited to word lines _L1 and _L2 , but the same applies to the other circuits. FIG. 2 is a timing chart for explaining the operation. The potential of the word line activation signal terminal P is V _CC +V _TH +α (here, V _CC
is the power supply voltage, V _TH is the threshold voltage of transistors Q ₁₁ and Q ₁₂ , and α is the margin voltage. ), and then when the power supply voltage V _CC is applied to the word line selection signal terminal D ₁ , the transistor Q ₁₁ turns on and transmits the activation signal to the word line L ₁ . At this time, the potential of the word line _L1 becomes V _CC and becomes "H".
As the potential of the word line _L1 rises, the transistor _Q31 starts to turn on, and when the potential of the word line _L1 exceeds the threshold voltage _VTH3 of the transistor _Q31 ,
The potential on reset line N drops from V _CC -V _TH4 (where V _TH4 is the threshold voltage of transistor _Q4 ) to OV. As the potential of the reset line N decreases, the transistor _Q21 begins to turn off, and becomes completely off when its potential falls below V _TH2 (here, V _TH2 is the threshold voltage of the transistors Q ₂₁ and Q ₂₂ ). Unselected word line selection signal terminal D ₂
is maintained at OV, transistor _Q12 is not turned on, and the potential of word line _L2 is OV.

Next, when a reset signal with a potential of V _CC is input to the reset signal terminal R, the transistor _Q4 is turned on, and the potential of the reset line N becomes V _CC -V _TH4.
The pressure is increased to And the potential of reset line N is
When V _TH2 or higher, transistors Q ₂₁ and Q ₂₂
turns on, and the potential of word line _L1 is reduced to OV. At the same time, transistor Q ₃₁ ,
_Q32 is turned off and the potential of reset line N is V _CC −V _TH4
calm down. In such an operation, the word line
L ₁ and L ₂ become "H" only when selected by the word line selection signal, and must remain in the "H" state until reset by the reset signal.

In the conventional circuit, transistors Q ₁₁ , Q ₁₂ , Q ₂₁ ,
There was a drawback that a leakage current was generated due to the short channel effect of Q ₂₂ , causing the "H" potential of word lines L ₁ and L ₂ to drop, and the potential of the word line activation signal to drop. As shown in FIG. 1, the transistors Q ₁₁ , Q ₁₂ ...Q _1o , Q ₂₁ , Q ₂₂ , ...
This drawback can be overcome by increasing the threshold voltage of Q _2o to prevent leakage current from occurring due to the short channel effect. (In FIG. 2, the dotted line shows a waveform diagram in the case where a potential drop is involved.) Therefore, normal memory write operation is not inhibited.

Note that the present invention is not limited to the circuit shown in FIG. 1; the gate length of the transistor that transmits the activation signal to the word line and the transistor that is connected to the word line and performs the reset operation can be changed to that of other transistors. All lengths compared to
Needless to say, it can be applied to a MOS type word line signal drive circuit.

(Effects) As explained in detail based on the examples above,
In this invention, the threshold voltages of the transistors constituting the circuit are made different to prevent the occurrence of leakage current due to the short channel effect, so the D-RAM can simultaneously satisfy the two requirements of high speed and good operating margin. It has the excellent effect of being able to realize the following.

[Brief explanation of drawings]

FIG. 1 is an example of a circuit connection diagram of a D-RAM to which the present invention is applied, and FIG. 2 is a time chart for explaining the operation of the circuit shown in FIG. 10...Reset circuit, 20...Memory section,
Q ₁₁ , Q ₁₂ , ...Q _1o ... Transistor with high threshold voltage (first transistor), Q ₂₁ ,
Q ₂₂ ,...Q _2o ...Transistor with high threshold voltage (second transistor), P...Word line activation signal terminal, _D1 , _D2 ...Dn...Word line selection signal terminal, _L1 , _L2 ...Ln...word line, R...
Word line reset signal terminal.

Claims (1)

[Claims] 1. A first MOS transistor that transmits a word line activation signal to the word line in response to a word line selection signal, and a first MOS transistor that resets the activation signal level of the word line in response to a reset signal. A MOS word line signal drive circuit comprising: a second MOS transistor connected to the word line in the reset circuit and resetting the activation signal level of the word line when the reset signal is applied; A MOS word line signal drive circuit characterized in that the gate length of the first MOS transistor is longer than the gate length of the transistors constituting the memory cell.