JPH0247573A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To perform testing efficiently even if the number of outer input/output terminals is few by providing a means which receives signals from two or more output terminals of a functional block under test in a time division mode at an outer output terminals. CONSTITUTION:Signals I1-I19 are inputted into a logic circuit 1. The signals are inputted into a functional block 3 through a selector circuit 2 which performs the switching of a test mode and a normal mode, and tests are carried out. The result of the test is outputted to the outside as O1 through an output selecting circuit 7 and a selector circuit 2'. At this time, the output selecting circuit 7 is selected with control signals S1-S3 one by one in a tie division mode. In this way, a semiconductor integrated circuit which can perform testing even if the number of outer input/output terminals is fewer than the number of the input/output terminals of the functional block 3 can be obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor circuits, and particularly to semiconductor integrated circuits in which blocks having a set of functions can be tested by dividing the circuit and directly controlling the blocks independently using external input/output terminals. Regarding circuits.

[Conventional technology]

Due to the remarkable development of integrated circuit technology in recent years, semiconductor integrated circuits are becoming larger and more complex.As a result, improvements in the testability of semiconductor integrated circuits and increased test efficiency are improving product reliability and cost. This has become one of the deciding factors.

Therefore, one method for improving circuit testability is to divide an integrated circuit into functional blocks such as RAM, ROM, or a collection of circuits with a certain set of functions. , a circuit partitioning method that performs functional verification of each division unit separately from feasibility verification of the entire circuit.

For example, as shown in Fig. 4, input signals 11 to 4 to the internal logic circuit 1 are normally input to the functional block 3 to be tested via the selector circuit 2, and the output terminal of the functional block 3 is directly input to the external input. It is connected one-to-one to the terminals 01 to 03, and is switched from the normal mode to the test mode by a TM signal applied to the test mode switching terminal, so that the function of only the functional block can be verified regardless of the function of the entire circuit.

Furthermore, in the case of a circuit that includes multiple functional blocks having the above configuration, the method of verifying another functional block after completing the verification of one functional block,
The number of test patterns increases and there is a possibility that the pattern will be limited by the tester, but in order to avoid this, a configuration as shown in FIG. 5 is adopted.

In FIG. 5, the functional blocks 31, 32 and 33 are selected almost simultaneously, and the functional blocks 31 include I+1 to 11.
From n, 32 includes I21 to I2n.

33 has 13□~d3. ．． Input signals are sent from OII to OIn and 021 to 0□, respectively. , 03. ~03
An output signal is output from n. In this case, since each test pattern can be input at the same time, it is possible to shorten the test pattern as shown in FIG.

[Invention or problem to be solved]

In the conventional technology described above, in which the external input/output terminals of a semiconductor integrated circuit and the input/output terminals of a selected functional block are connected one-to-one, the number of input/output terminals of a functional block is limited to the number of external input/output terminals that can be used for testing. If there are more external input/output terminals for testing, and if it is impossible to add more terminals due to the number of bins limited by the package,
The drawback is that it is not possible to test functional blocks.

In addition, in order to select and test multiple functional blocks almost simultaneously to shorten the test pattern, connect other functional blocks and external input/output terminals on a one-to-one basis, and then connect the remaining external input/output terminals to another one. When trying to connect functional blocks one-to-one, if the number of remaining external input/output terminals is less than the number of input/output terminals of the functional block, the remaining functional blocks cannot be connected and will not connect with other functional blocks. Since it is no longer possible to test almost simultaneously, the remaining functional blocks must be tested after other functional blocks have been tested, resulting in an increase in the number of test patterns.

[Means to solve the problem]

In the semiconductor integrated circuit of the present invention, in a semiconductor integrated circuit including functional blocks, at least two or more outputs of the functional blocks are connected to an external output terminal for directly outputting test signals of the functional blocks to the outside. and means for inputting signals from the terminals in a time-division manner.

〔Example〕

The present invention will be explained below with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention.

The -I19 signals input to the logic circuit 1 are used as test input signals to the functional block 3, and switching between the test mode and normal mode is performed via the selector circuit 2 under control by the TM signal.

The test results from the functional block 3 are input to the output selection circuit 7, selected one by one using control signals 81 to S3, and outputted to the outside as the O1 signal via another selector circuit 2'.

In this embodiment, the function block 3 has eight outputs, and originally eight external output terminals would be required, but a total of four, consisting of three control signals and one external output terminal, is sufficient. External terminals for testing can be reduced. Further, although a method is adopted in which the signal is output using one external output terminal, a plurality of external output terminals may be used. For example, when outputting with 2 external output terminals, 2 controls are required (4 total), and the function is to reduce 4. When outputting with 4 external output terminals, 1 control and 4 are required. A total of 5 pieces are required, and it is possible to reduce the number by 3 pieces.

FIG. 2 is a circuit diagram of a second embodiment of the invention.

In this embodiment, the circuit has m functional blocks 31 to 3m.
The test pattern is shortened by using a method that selects and tests multiple functional blocks almost simultaneously.

First, function blocks 31 and 32 are selected simultaneously by signal 81, and input signals I11 to ■1□
and ■2□ to I2n are input almost simultaneously to 32, and 01□ to o ln+021 are respectively inputted via the output selection circuit 7.
~0□. Output the test results from.

At this time, the ■5□ to 5° signals are input to the function block 35 at the same time, and the test result of 35 is sent to another output selection circuit 7'.
is input to S2. It is selected by the S3 signal and output from 05.

Next, switch the 81 signal, select function blocks 33 and 34, and 33 contains I11 to ■1. , signal, 34 is I21
~I2n signals are respectively input, and similarly to 31°32, 011~OIn and 021~0□, respectively. Output the test results from.

FIG. 3 is a model of a test pattern corresponding to this circuit.

The test pattern is shortened compared to the case where the test pattern for each functional block is serially tested.

〔Effect of the invention〕

As explained above, the semiconductor integrated circuit of the present invention is configured such that test signals from at least two output terminals of a functional block to be selected and tested can be time-divisionally input to one external output terminal. This configuration has the effect of enabling testing even when the number of external input/output terminals that can be used for testing is less than the number of input/output terminals of the functional block.

In addition, in order to shorten the length of the test pattern, when at least two or more functional blocks are selected and tested almost simultaneously, the input/output terminals of other functional blocks and the external input/output terminals are connected on a one-to-one basis. If the number of remaining external input/output terminals is less than the number of input/output terminals of the remaining functional blocks after connecting with This is even more effective.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a first embodiment of the present invention, Fig. 2 is a circuit diagram of a second embodiment of the invention, Fig. 3 is a model diagram of the test pattern shown in Fig. 2, and Fig. 4 5 is a circuit diagram of the first conventional example, FIG. 5 is a circuit diagram of the second conventional example, and FIG. 6 is a model diagram of the test pattern of FIG. 1...Logic circuit, 2.2'...Selector circuit, 3
1 to 35...Functional block, 4...Pre-stage circuit, 5.
...Normal output, 6...Normal input, 7,7'...Output selection circuit, 8...Decoder PIal I...Manual test pattern for the entire circuit,
POall...Test pattern of expected output value of the entire circuit, PI, ~3. PI31~pr3. ... Function block input test pattern, Po1~PO5゜PO3,~
P○3.・Test pattern for the expected output value of the functional block.

Claims (1)

[Claims] In a semiconductor integrated circuit including a functional block, signals from at least two or more output terminals of the functional block are input in a time-sharing manner to an external output terminal for directly outputting a test signal of the functional block to the outside. A semiconductor integrated circuit characterized by having means.