JPH0247742A - Busy time control system - Google Patents

Abstract

PURPOSE:To reduce hardware by subtracting the constitution number of the finally accessed bank from a numerical value corresponding to BANK BUSY- TIME and generating a signal BANK-BUSY for a time corresponding to the numerical value obtained by adding the number of the first accessed bank to the subtraction result. CONSTITUTION:START-BANK-ID for the start of access is set to '0', and BANK-BUSY-TIME is set to 10tau, and '5' of LAST-BANK-ID at the time of generation of a signal REQUEST-END from the external is set to a counter 1. A subtracting device 2 subtracts fixed value '9' from the output value of the counter because BANK-BUSY-TIME is 10tau. In a comparing circuit 3, the signal BANK-BUSY is generated when the subtraction result is smaller than START-BANK-ID.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a method for controlling access to a storage device when the storage device is composed of a plurality of banks. In order to eliminate the necessary bank busy decoding generation circuit and reduce hardware, the last bank to be accessed among multiple banks that are sequentially accessed is installed in the control device that controls access requests. a counting circuit whose initial value is the configuration number of the bank, means for subtracting a fixed value corresponding to a predetermined fixed time from the counted value of the counting circuit, and comparing the subtraction result with the configuration number of the first accessed bank. and a means for doing so.

[Industrial application field]

The present invention relates to a control method for access requests to a storage device, and more particularly to a control method when a storage device is composed of a set of banks and a plurality of banks are accessed consecutively.

[Conventional technology]

A bank (hereinafter also referred to as BANK) which is a partial storage device in the storage device is being accessed (hereinafter referred to as -Btl in BAN).
Bank busy signal (hereinafter also referred to as BANK-BUSY signal) to notify the outside of the SY state (also referred to as SY state)
Bank busy time (hereinafter referred to as BANK
A circuit for generating a signal (also referred to as -BUSY-TIME) has conventionally had a configuration as shown in FIG.

FIG. 5 shows a conventional bank busy time signal generation circuit, in which 51-1 to 51-n, 53-1 to 5
3-n represents an AND circuit, and 52-L to 52-n represent subtraction counters. To explain the operation below, first, the BANK configuration number (hereinafter also referred to as BANK-ID) is "00'" BAN (hereinafter referred to as BANK-ID).
=OO) is accessed, signal B on the diagram
ANK-lo-00 and signal SET "9' set the value "9" in the counter 52-1 through the AND circuit 51-1.
It is a counter that subtracts 1, and the output of the signal ALL "0" becomes true after 10 clocks, that is, 10τ.Therefore, when the "00'th BANK is accessed, the BAN becomes -BUSY for 10τ. , the next access request will not be accepted, and after 10τ it will be possible to accept the -IQ-00 signal to NEIXTBAN, which is the next access request, and BANK-In00-ACCESS-0 for access permission will be accepted through the AND circuit 53-1. give a signal.

The above operation is the same for the other BANK-01~mouth.

[Problem to be solved by the invention]

Traditional method, BANK BIJSY TIME! The circuit for generating is a counter for each BANK. , makes the next access to the same BANK wait.

In this method, a counter consisting of a plurality of bits is installed for each incoming NK, so if the BANK width is wide, the amount of attached hardware becomes enormous.

The present invention has been made in consideration of the above problems, and therefore a plurality of B.
The purpose of this invention is to eliminate the counter provided for each BANK and reduce the amount of hardware when ANKs are accessed consecutively in the order of their configuration at a relatively high frequency.

In a computer system that is basically accessed sequentially starting with the lowest configuration number, the control device that controls access requests has a unit that uses the configuration number of the last bank among the multiple banks as an initial value. a counting means for performing unit addition for each time; and means for subtracting a numerical value corresponding to a predetermined fixed time from the counted value of the counting means;
[Means for Solving the Problem] According to the present invention, the busy time control method is characterized by providing a means for comparing the subtraction result with the identification number of the bank to which access is first started. The object is achieved by the measures defined in the claims.

That is, in the present invention, a storage device is constituted by a set of banks called partial storage devices, the storage device receives access requests from a plurality of access sources, and furthermore, the plurality of banks in the storage device are sequentially and sequentially accessed. When accessed, the storage device is composed of a set of many BANKs, and the BANKs are accessed.
NK-BUSY-TIM day (7) measurement and BANK B
[In order to generate the ISY signal, a counter with sufficient bit width to count the BANK width is provided, the initial value of the counter is the configuration number of the BANK that was last accessed, and "+" is set every unit time τ.
Add 1″ at a time, and from the value of the counter, BANK
BANK-BUS has an access time unique to
Means is provided for subtracting a numerical value corresponding to Y-TIMB and comparing the result of the subtraction with the configuration number of the bank whose access is first started, thereby generating a BUSY TIME signal. That is, BANK-B, which is the bank's unique access time
The BANK-BtlSY signal is generated for a time corresponding to the value obtained by subtracting the configuration number of the last accessed bank from the value corresponding to tlSY-TIME and adding the number of the bank that was first accessed to the result. It is something that makes you

〔Example〕

FIG. 1 shows one embodiment of the present invention, and shows a BA according to the present invention.
This shows a block diagram of the NK-B [ISY signal generation circuit, where 1 is an addition counter, 2 is a subtracter, 3 is a numerical comparator, and 4
represents a flip-flop, and the signal name, AST
"BANK-[0 is the number of the last BANK that is accessed continuously, 5 TART-BAN - 1D is the number of the first accessed RAN, 10 [
ISY represents a signal that informs the outside that the bank is being accessed.

The configuration and operation of this embodiment will be described below.

In order to generate the BANK-BUSY signal when each bank in the storage device is accessed sequentially and consecutively with a relatively high frequency, the RIliOU8ST-END signal (not shown in the figure) is used to notify the end of an external access request. do not)
Configuration number of BANK in memory at the time of occurrence (BANK-IQ
) as LAST-BANK IQ, and the BANK-IQ
A counter will be provided that uses human power.

Furthermore, installing a subtraction device 2 for subtracting the output of the counter and a fixed value corresponding to BANK-BUSY-TIME (determined by the hardware configuration of BANK);
and the output of said subtraction device 2 (indicated by symbol a on the diagram)
, BANK-IQ is 5TA when access is started.
RT-BANKiD (indicated by the symbol CDMP in the figure) is compared with the comparator 3 (indicated by the symbol CDMP in the figure), and from the subtraction result of the subtractor 2, 5TART-BANK
When -In shows a larger value (that is, a>b), it is in the BANK-BUSY state.

A specific example of the operation in FIG. 1 will be explained.

First, BANK-In (ST
ART-BANK-1n) '0'', BANK-8US
Y-TIME 10τ, outside B Kara (7) REQUE
BANK-1n (LAST-
BANK-10) is assumed to be 5''.

First, "5'" which is LAST-BANK-10,
It is set in the counter, and the count value is 5 → 6 → 7-8
→9→10...

In the next subtraction device 2, BANK-BtlSY-TIME
10τ", the fixed value "9" is subtracted from the output value of the counter, and the subtraction result is -4→-3→-
2→-1-0-1...

Furthermore, the comparison circuit 3 compares 5RART-BAN with "0", which is -IQ, and the subtraction result is < 5TART-B.
When NKIn is reached, the 8ANK-[]IJSY signal is generated.

The state of this operation is shown in a table in FIG.

FIG. 2 shows subtractor 2,
Comparator 3, the state of change of the -BIJSY signal to BAN is summarized in the table, and the BANK-BUSY signal is 5τ
After waiting time (llait time), signal-bin becomes A
An ND circuit is shown.

BANK-B [ISY signal is used with inverted logic and is an access request signal to the BAN making the next access request, NE
XT-BANK-IQ-00~On and AND circuit 5-1
A logical AND is performed with ~5n, and an access permission signal BANK-10-00-ACC[1SS-0 for each BANK is generated ~BAN-In-OnACCESS-OK.

FIG. 4 is a time chart showing the bank busy state, and BANK-10 is “00” when access is started.
And from the outside (7) RBOIIEST-END 4
AST-BANK-1 when No. M (not shown) occurs
This is an example in which 0 is set to 05''.

The storage device is accessed sequentially from RAN queries 0 to 05, and the last accessed BAN is accessed at point a to BAN -05, and each RAN is in a BUSY state! ! 6
-Q ~6-51. : Enter, BANK-BUSY-TI
ME (D measurement starts, on this BAN-BtlSY
-BA whose configuration number is “00” during TIME measurement
Even if an access request is made to NK-00 at point b, the request will not be accepted, and 88 NK-00 will be able to accept the access request from point 0, which is 5τ after point a. 8^NK-BtlSY indicated by 7 when the receiver is attached
enter the state of

In the above specific example, the In of the first BANK to which access is started is set to "001st," but of course, access can be started by any numbered BAN, and any number consecutive from the bank to which access is started is possible. You may end with a bank of

This results in a significant reduction in hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a bank busy signal generation circuit according to the present invention, FIG. 2 is an operation state table of the bank busy signal generation circuit, FIG. 3 is a circuit for generating access permission signals for each bank according to the present invention, and FIG. 4 5 is a time chart showing a bank busy state, and FIG. 5 is a conventional bank busy time generating circuit. 1...Addition counter, 2...Subtractor, 3...Numeric comparator, 4...Flip-flop, 5-1 to 5-n-・・・-・-A N D
Circuit, 6-0 to 6-5.7...-Bt to BAN
lSY state [Effect of the invention] A counter consisting of multiple bits and its attached circuit, which were conventionally required for each bank, is no longer necessary. Patent applicant Kozo Iizuka, Director of the Agency of Industrial Science and Technology @) Koyoro Access permission to each pack No. 4) /￥Nari vJ departure diagram

Claims (1)

[Scope of Claims] A storage device is constituted by a set of banks called partial storage devices, the storage device receives access requests from a plurality of access sources, and furthermore, a plurality of banks in the storage device are successively accessed. In a computer system that is basically accessed sequentially starting from the lowest configuration number among the plurality of banks, the above-mentioned plurality of banks are installed in a control device that controls access requests from the access source. counting means for performing unit addition every unit time using the configuration number of the last bank of the banks as an initial value; means for subtracting a numerical value corresponding to a predetermined fixed time from the count value of the counting means; and a result of the subtraction. A busy time control method comprising means for comparing identification numbers of banks to which access is first started.