JPH0247778B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system, and more particularly, to a slave central processing unit (hereinafter referred to as
Abbreviated as CPU. ) relates to a multiprocessor system in which a main CPU always accurately executes an abnormality processing routine regarding a slave CPU when an abnormality occurs in a cycle in which a main CPU occupies the main bus.

[Prior art] In a conventional multiprocessor system consisting of a main CPU and a slave CPU, the slave
If any abnormality is detected during a cycle in which the CPU is using the main bus, an interrupt is generated and the abnormality handling routine of the slave CPU is executed by the main CPU.

[Problem to be solved by the invention] However, in this case, even if an abnormality is detected and an attempt is made to jump to the abnormality processing routine, the main CPU itself is halted and its operation is stopped. Unable to execute error handling routine. Also, as a result of the abnormality, the slave CPU cannot execute the process. Therefore, both the main and slave devices remain inactive, causing the entire system to stop functioning.

The present invention eliminates the above-mentioned drawbacks, and in a multiprocessor system, whenever an abnormality is detected during the slave CPU cycle, the main
The object of the present invention is to provide a device in which an abnormality handling routine is executed by a CPU.

[Means for Solving the Problems] The present invention provides: a main CPU that uses a main bus; a slave CPU that uses the main bus; and a ratio at which the main CPU and the slave CPU occupy the main bus. a main bus occupancy setting means, detecting an error that occurs while the slave CPU is using the main bus, setting the main bus occupancy ratio of the slave CPU to 0 at the same time as detecting the error, and further responding to the error. an abnormality detection means for outputting a signal instructing the generation of an interrupt signal, and a signal for instructing initialization to the means for controlling the main CPU in response to the output signal from the abnormality detection means; If the main CPU is in a halt state, the main CPU is controlled to release the halt state.

[Example] In the present invention, when an abnormality occurs in a cycle in which the slave CPU occupies the main bus, the abnormality detection circuit detects it and further operates the register controlling the main CPU, and the slave CPU
Set the main bus occupancy rate of the CPU to 0 and use the main CPU
ensures that the slave CPU's error handling routine is executed.

The present invention provides a main bus occupancy setting register that stores a variable value for determining the occupancy of the slave CPU on the main bus, and connects the main CPU and the slave CPU to the main bus. a bus multiplexer to disconnect;
A function to detect that an abnormality has occurred on the main bus, a function to latch the state at the time of the abnormality in the recovery processing register when an abnormality is detected, and a function to simultaneously clear the main bus occupancy rate setting register. and a function of inputting a trigger signal to an interrupt generation circuit for generating an interrupt to the main CPU; and an abnormality detection circuit that is connected to the main bus, controls the main CPU, and is further cleared by a signal from the interrupt generation circuit. The slave CPU control register is connected to the main bus and controls the slave CPU.

FIG. 1 is a block diagram schematically showing one embodiment of the present invention. Main CPU1 and slave CPU2
is selectively connected to or disconnected from the main bus 7 by the bus multiplexer 5. Also, slave
The ratio at which the CPU 2 occupies the main bus 7 is determined by a bus multiplexer ratio (hereinafter abbreviated as BMR) register 6.

This BMR register 6 is used to optimize the occupancy rate of the main bus 7. For example, if the load on the main CPU 1 is large and the slave CPU
When the load on the main bus 7 is small, the value of this BMR register 6 is small (i.e., when the load on the main bus 7 is small).
The goal is to increase the occupancy rate of the main CPU 1 and reduce the occupancy rate of the slave CPU 2. )
It is possible to synchronize the processing of the main CPU 1 and slave CPU 2.

The abnormality detection circuit 3 detects an abnormality on the main bus 7 and further outputs a trigger signal 36 to an error code register (hereinafter abbreviated as ECR register) 22 to latch the abnormal state of the bus in the ECR register 22. Instruct. ECR register 22 uses signal 32 to latch an abnormal condition.

Main processor control register (below)
Abbreviated as MCR register. ) 21 is for directly controlling the main CPU 1 by a signal 34. To explain further, the main CPU 1 uses the main CPU control signal 31 on the main bus 7.
The contents of the MCR register 21 are manipulated, and the main CPU 1 is controlled again based on the manipulated results. In other words, the main CPU 1 controls itself via the MCR register 21. Further, the slave processor control register (hereinafter abbreviated as SCR register) 23 is a register that controls the slave CPU 2 by a signal 39, and its contents are as follows: use and operate.

Further, the interrupt generation circuit 4 generates an interrupt generation signal 35 based on the signal 38 from the abnormality detection circuit 3.
Input to MCR register 21 and main CPU 1,
Clear MCR register 21 and then clear the main CPU
1 to generate an interrupt. Further, the memory 8 is a shared memory between the main CPU 1 and the slave CPU 2 connected to the main bus 7.

Next, the operation of the present invention will be explained using FIG.
First, if an error occurs in a cycle in which the slave CPU 2 occupies the main bus 7, the error detection circuit 3
detects this and instructs the ECR register 22 by signal 36 to latch the state of the bus at the time of the error. Therefore, ECR register 22
uses signal 32 to connect main bus 7 when an error occurs.
Latch the state. At the same time, the abnormality detection circuit 3 issues a signal 37 to clear the BMR register 6, and further inputs a signal 38 to the interrupt generation circuit 4. Here, if the BMR register 6 is cleared, the main bus occupancy rate of the slave CPU 2 becomes 0, so the main bus 7 will be completely occupied by the main CPU 1 from then on. Further, upon receiving the signal 38, the interrupt generation circuit 4 sends the interrupt generation signal 35 to the MCR register 2.
1 and main CPU1. For this reason, MCR
Register 21 is cleared and main CPU 1
will be interrupted. Here, before the abnormality occurs, the main CPU 1 uses the main bus 7 and the main CPU control signal 31 to control the MCR.
If a flag is set in one bit of the register 21 to put a halt on the CPU itself, the MCR register 21 will be cleared by the interrupt generation signal 35 from the interrupt generation circuit 4, so that until then the main CPU 1 The halt will be canceled when an abnormality is detected.

As mentioned above, since the main CPU 1 is released from the halt state, the abnormality that occurred in the bus cycle of the slave CPU 2 is detected based on the information held in the ECR register 22 after receiving the interrupt request mentioned above. Restoration work can be carried out.

Also, in this recovery process, if necessary,
CPU1 receives SCR via main bus 7 and signal 33.
It is possible to initialize the slave CPU 2 by setting a flag in one bit of the register 23.

[Effects of the Invention] As explained above, in the present invention, for example, if an abnormality occurs in a cycle in which the slave CPU occupies the main bus, the abnormality detection circuit detects it, and The main interrupt generation circuit sets the occupancy to 0 and is activated by the abnormality detection circuit.
The configuration allows interrupts to the main CPU by clearing the main CPU control register that controls the CPU.

Therefore, according to the present invention, if an abnormality is detected in a cycle in which the slave CPU occupies the main bus, even if the main CPU has been in a halt state until then and the main CPU is in a stopped state. Since the main CPU is interrupted after being released, in the above case, the main
The CPU can always accurately execute the error handling routine of the slave CPU, and the main CPU continues processing without being restricted by the error in the main CPU, resulting in a significant improvement in the reliability of the entire system.

Further, the present invention further provides a method for providing a signal instructing initialization to the means for controlling the main CPU in response to an output signal from the abnormality detecting means.
If the CPU is in a halt state, control the main CPU to release the halt state.
Therefore, when an error is detected, the means for controlling the main CPU is initialized, the information that had previously instructed the main CPU to be halted is cleared, and the halt state of the main CPU is released.
Therefore, after an error occurs, error handling by the main CPU can be reliably executed, greatly improving system safety and reliability.

Also, a means of controlling the main CPU (e.g.
Since the MCR register 21 in FIG. 1 is cleared, the main CPU will be started from the initial state in error processing. Therefore, the main CPU can execute the next error process without being affected by the error at all (because it starts from the initial state). Therefore, error processing can be executed reliably.

Further, at the time when the main CPU starts error processing, the means for controlling the main CPU has been initialized. Therefore, for example, a keyboard,
Interrupts from the FDD, etc. are prohibited (by the initialization), and error processing interrupts are reliably accepted by the main CPU. Therefore, when an error occurs, the main CPU can quickly perform error processing.

Further, at the time when the main CPU starts error processing, the information held by the means for controlling the main CPU is always a predetermined value (initialized value). Therefore, the main CPU does not need to check each time the contents of the information held by the means for controlling the main CPU when executing error processing. Therefore, the control program for error handling of the main CPU can be greatly simplified.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of one embodiment of the present invention. 1...Main CPU, 2...Slave CPU, 3
... Abnormality detection circuit, 4 ... Interrupt generation circuit, 5
...Bus multiplexer, 6...BMR register.

Claims (1)

[Scope of Claims] 1. A main CPU that uses a main bus, a slave CPU that uses the main bus, and a main bus occupancy rate setting means that sets a ratio at which the main CPU and the slave CPU occupy the main bus. and detecting an error that occurred while the slave CPU was using the main bus, setting the main bus occupation ratio of the slave CPU to 0 at the same time as detecting the error, and further generating an interrupt signal in response to the error. abnormality detection means for outputting an instructing signal; and a signal for instructing initialization to be given to the means for controlling the main CPU in response to the output signal from the abnormality detection means, and the main CPU is in a halt state. A multiprocessor system characterized in that the main CPU is controlled to release the halt state if the main CPU is in the halt state.