JPH0247784B2 - BEKUTORUDEETAISOHOSHIKI - Google Patents

Description

[Detailed description of the invention]

(Technical Field to which the Invention Pertains) The present invention relates to a method for transferring vector data between vector registers in a vector data processing device, and more particularly to address control for reading and writing data in vector registers. (Prior Art) In conventional vector data processing devices of this type, reading of elements from a vector register or writing of elements to a vector register is generally performed serially. In such a vector data processing device, transfer control of vector data between vector registers can be easily performed. However, in order to perform high-speed processing, it is desirable to be able to read or write a plurality of elements from the vector register in parallel; however, in this case, there is a drawback that the control of read or write addresses given to the vector register becomes complicated. (Object of the Invention) An object of the present invention is to provide a vector data transfer method that eliminates the above-mentioned drawbacks and transfers vector data between vector registers in parallel and at high speed using relatively simple address control. . (Structure of the Invention) The vector data transfer method of the present invention performs at least one of reading 2 ⁿ (n1) elements in parallel and writing 2 ^m (m1) elements in parallel during one cycle. A plurality of vector register means, 2 ⁿ read data bus means provided corresponding to each read element of the vector register means, and 2 ^m write data bus means provided corresponding to each write element. and data aligning means capable of arbitrarily connecting the read data bus means and the write data bus means, wherein the vector register means performs reading and the vector register means performs writing, respectively. Means for dividing binary numbers indicating start addresses of reading and writing corresponding to all elements of and means for controlling the connection of the data aligning means using the lower bit groups i and k, and upper bits for a predetermined read element indicated by the lower bit group i as a read start address of the vector register means for reading. means for giving a value in which 1 is added to group j and giving upper bit group j to other read elements; and a predetermined write element indicated by lower bit group k as a write start address of the vector register means for writing The present invention is characterized in that it includes means for giving a value in which 1 is added to the upper bit group l, and giving the upper bit group l to other write elements. (Embodiments of the Invention) Next, the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, one embodiment of the present invention has vector registers 100 and 200 that can read and write four elements simultaneously, and each vector register 100 and 200 has four read data buses 1100-1130 and 1200-
1230 and write data bus 2100-2130
and 2200-2230 are connected,
Connection between the read data bus and the write data bus is performed in data align circuit 600 by a control signal applied from control section 300 via control bus 3000. In addition, one embodiment includes a read start address generation section 400, a write start address generation section 500, read start address buses 4100 and 4200, write address buses 5100 and 5200, a control section 700, and control buses 7100-7500. There is. Second
Referring to the figure, in this embodiment, the vector register 100 or 200 is divided into four vector registers VR10-VR13 (or VR20-
VR23) and their corresponding read address counters RA10-RA13 (or RA20-
RA23) and write address counter WA10-
WA13 (or WA20-WA23). Also, the control bus 7100 (or 720
0), read address counters RA10-RA13 (or RA20
-RA23), write address counter WA10-
Write enable/disable control of read/write start address for WA23 (or WA20-WA23), count up control, and vector register VR
Write permission control for 10-VR13 (or VR20-VR23) is performed. Referring to FIG. 3, the data alignment unit 600 includes read data buses 1100-1130 and 1200-123.
0 is connected to the write data bus 2100 via the selection circuit SE10, and the vector register
Any read element of VR10-VR13 and VR20-VR23 can be used as a write element of vector register VR10. Although not shown in the diagram, selection circuits SE10-SE13 and SE20-
A read data bus is similarly connected to SE23. In addition, selection circuits SE10-SE13,
SE20-SE23 are controlled by control bus 3000. Referring to FIG. 4, the read start address generation unit 400 includes an adder 410 that adds "1" to the upper bit group of the read start address for all elements of the vector register given via the line 41; The address bus 4100 and 4 select either the value that is added to the upper bit group that is the output of the upper bit group and output on the line 42, or the value on the line 41 that is the upper bit group, and start reading.
vector registers 100 and 2 through 200
00 read address counter RA10-RA1
3. Selection circuit 42 sending to RA20-RA23
0-423 and 430-433, and the lower bit group (2 bits in the case of this embodiment) given via the line 43 are decoded and sent to the selection circuits 420-42.
3 and 430-433.
Consists of 0. The relationship between the lower bit group given via this line 43, the upper bit group on the line 41 selected by the selection circuits 420-423 and 430-433, and the upper bit group added "1" on the line 42 is expressed as follows. Shown in the table.

[Table] The write address generation unit 500 also has the same configuration as the read address generation unit 400, and the input data is the write start address for all elements, and the write address generation unit 500 has the same configuration as the read address generation unit 400.
Output data for. Next, the operation of this embodiment will be explained in detail below. Referring to FIG. 5, vector register 100
7th vector element a ₆ to vector element a _k-9
Store v _l vector elements up to vector register 2
The case of transferring to the 10th and subsequent numbers of 00 will be explained as an example. The read start address for all elements of the vector register is '0...00110', and the write start address is '0...01001'. Furthermore, when the vector elements in FIG. 5 correspond to the block diagram of the vector register shown in FIG. 2, the vector elements are divided into four parts and stored respectively as shown in FIG. 6. In this case, the read start address generation unit 40
0 receives the read start address '0...00110' and divides into upper bit group '0...001' and lower bit group '10', and uses lower bit group '10' to read address counters RA10, RA11, RA20 and RA2.
The value '0' obtained by adding "1" to the upper bit group for 1
...010' and sends the upper bit group '0...001' to read address counters RA12, RA13, RA22 and RA23, and controls whether or not to write to the read address counters given via control buses 7100 and 7200. Therefore, the read address counter RA10-RA of the vector register 100, which is a read vector register.
Write only to 13. Similarly to the read start address generation section 400, the write start address generation section 500 also receives the write start address '0...01001' and divides it into an upper bit group '0...010' and a lower bit group '01'. By '01', the value '0...011' obtained by adding '1' to the upper bit group is written to the write address counter WA20, and the write address counters WA21, WA22 and WA2
3, write the upper bit group '0...010'. Therefore, the reading and writing start addresses of each divided vector register are at the positions indicated by arrows in FIG. Further, the lower bit group indicates a divided vector register containing the first vector element for each read and write. In this case, the lower bit group for reading is '10', so the divided vector register containing the 7th vector element is register VR12, and the lower bit group for writing is '01', which is the 10th vector element. The included divided vector register is register VR11 or VR21. Therefore,
The data alignment control unit 300 receives information indicating the two lower bit groups related to this address, the vector register to be read from, and the vector register to be written to, and creates a VRxy having the first vector element to be transferred and writes it. The data aligning unit 60 connects VRvw, connects VRxy' having the second vector element, and VRvw' that writes it, and similarly connects the third and fourth vector elements.
0 connection control. In this case the register
VR12 and VR21, VR13 and VR22, VR14
and VR23, and VR11 and VR24 are connected via a data alignment section 600. When the above operations are completed, the control unit 700 repeatedly instructs the vector register to write a vector element and instructs the read address counter and write address counter to count up, thereby transferring the vector element. In this case, if v _l is '0...0110101', four elements are transferred in parallel, so the value of v _l /4+1 is '0...
0110' is the number of writes. Therefore, in operation, first four elements a ₈ , a ₉ , a ₆ , a ₇ are written to the transfer vector register 200, then a ₁₂ , a ₁₃ , a ₁₀ ,
Thereafter, the four elements of a ₁₁ are transferred and written in order. But in the last 14th time a _k-7 ,
Four elements a _k-6 , a _k-9 , and a _k-8 are transferred, but the element written is the element written to register VR12.
a _k-9 only, and writing to registers VR20, VR22, and VR23 is suppressed and not written. This write inhibition control is performed from the divided vector register indicated by the lower bit group of the write start address for all elements of the vector register _.
This is done by allowing writing to only the number of divided vector registers indicated by the lower two bits of . In other words, in this case, the lower bit group of the write start address is '01', so register VR2
1, and the lower two bits of v _l are '01', so only register VR21 is writable. Table 2 shows the relationship between the lower bit group of the write address, the lower 2 bits of _vl , and write permission in the write inhibition control performed during the last write.

[Table] 1: Write enabled 0: Write inhibited These series of operations complete the transfer of vector data between vector registers. (Effects of the invention) As can be seen from the above, this vector data transfer method allows transfer with the minimum number of transfers as follows: Number of transfers = Number of vector elements to be transferred/Number of vector elements that can be transferred in parallel + 1 (times) This has the effect that all the transferred vector elements can be written except for the last writing, and that even at the final writing, a simple control of only inhibiting writing to some vector registers is required. Furthermore, if the read start address or write start address is fixedly determined, a corresponding start address generation section is not required, and the control becomes simpler than data alignment and write inhibition control.

[Brief explanation of drawings]

1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a detailed configuration of the vector register section 100 or 200 shown in FIG. 1, and FIG. 3 is a diagram showing a detailed configuration of the data alignment section 300. FIG. 4 is a diagram showing the detailed configuration of the read start address generation section 400, and FIGS. 5 and 6 are diagrams for explaining the operation of the present invention. In Figures 1 to 6, VR10 to VR1
3...Vector register, WA10 to WA13...
...Write address counter, RA10 to RA13
...Read address counter, SE10 to SE1
3, SE20 to SE23...selection circuit, 300...
Data alignment control decoder, 410... Adder, 420-423, 430-433... Selection circuit, 440... Decoder, 1100-1130,
1200-1230...read data bus, 21
00-2130, 2200-2230...Write data bus, 4100,4200...Read start address bus, 5100,5200...Write start address bus, 3000,4300,530
0,7300...Data alignment control bus, 71
00,7200...Vector register control bus,
7400... Read start address generation unit control bus, 7500... Write start address generation unit control bus, 41, 42, 43, 44... lines.

Claims (1)

[Scope of Claims] 1. A plurality of vector register means for performing at least one of parallel reading of 2 ⁿ (n1) elements and parallel writing of 2 ^m (m1) elements in one cycle; 2 ⁿ read data bus means provided corresponding to each read element of the vector register means; 2 ^m write data bus means provided corresponding to each write element; and the read data bus means. and data aligning means to which the write data bus means can be arbitrarily connected, the vector register means for reading and the vector register means for writing; The lower bit group i(n
bit), upper bit group j, lower bit group k(m
means for controlling the connection of the data alignment means using the lower bit groups i and k; and means for controlling the connection of the data aligning means using the lower bit groups i and k, and using the lower bit group i as a read start address of the vector register means for reading. means for giving a value obtained by adding 1 to the upper bit group j to the indicated predetermined read element and giving the upper bit group j to the other elements; and the lower bit group k as a write start address of the vector register means for writing 1. A method for transferring vector data between vector registers, characterized in that the method includes means for giving a value obtained by adding 1 to a group of upper bits l to a predetermined write element indicated by , and giving a value of l to a group of upper bits to other write elements.