JPH0247852A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0247852A
JPH0247852A JP19913088A JP19913088A JPH0247852A JP H0247852 A JPH0247852 A JP H0247852A JP 19913088 A JP19913088 A JP 19913088A JP 19913088 A JP19913088 A JP 19913088A JP H0247852 A JPH0247852 A JP H0247852A
Authority
JP
Japan
Prior art keywords
wiring
film
forming
insulating film
silicon oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19913088A
Other languages
Japanese (ja)
Inventor
Kazuhiko Katami
形見 和彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP19913088A priority Critical patent/JPH0247852A/en
Publication of JPH0247852A publication Critical patent/JPH0247852A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve the reliability by forming a conductive film projection and an interlayer insulating film made of a material different from a first wiring at the part, where a concrete hole is formed, of said wiring, flattening the surface and exposing the projection at the same time, forming a second wiring thereon, and conductively connecting the second wiring with the first wiring. CONSTITUTION:A tungsten film 104 is formed on a silicon oxide film 102 including a first wiring composed of an aluminum-silicon alloy film 103 on a semiconductor substrate 101, and then photoetching is performed except for only the part which becomes a contact hole. A silicon oxide film 105 as an interlayer insulating film is formed. A photoresistor 106 is applied by rotation and the surface is flattened. Etching is performed until the silicon oxide film 105 on the tungsten film 104 is completely eliminated to expose the tungsten film 104. And then second wiring composed of an aluminum-silicon alloy 107 is formed and connected with the first wiring. This improves the yield and the reliability.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、多層配線を有する半導体装置における各配線
層間の相互接続方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for interconnecting wiring layers in a semiconductor device having multilayer wiring.

[従来の技術] 従来の半導体装置の製造方法では、最初第2図(a)の
ように、第1の金属配線203の形成された半導体基板
201上方に眉間絶縁膜204を形成した後、第2図(
b)のように、フォト・エツチングにより眉間絶縁膜2
04にコンタクトホールを開孔し、最後に、第2図(C
)のように。
[Prior Art] In a conventional method for manufacturing a semiconductor device, as shown in FIG. Figure 2 (
As shown in b), the insulating film 2 between the eyebrows is formed by photo-etching.
04, and finally, as shown in Fig. 2 (C
)like.

第2の金属配線205を形成し、第1の金属配線203
と第2の金属配、111205は互いに電気的に接続さ
れるようになっていた。このとき、一般にはコンタクト
ホールのエツチングはドライエツチングで行ない、また
、配線金属はスパッタ法により形成している。
Forming the second metal wiring 205 and forming the first metal wiring 203
and the second metal interconnect, 111205, were to be electrically connected to each other. At this time, contact holes are generally etched by dry etching, and wiring metal is formed by sputtering.

[発明が解決しようとする課題] しかしながら、前述の従来技術では、パターンが微細化
されるにともないコンタクトホール部分での配線金属の
被覆性が乏しくなり、最悪の場合にはこの部分で第2の
金属配線が断線する場合があった。また、眉間絶縁膜表
面の凹凸に起因する段差も急峻になり、この部分におい
て第2の配線金属が断線したり、逆に隣接する配線間で
短絡したりする場合があった。
[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, as the pattern becomes finer, the coverage of the wiring metal in the contact hole portion becomes poor, and in the worst case, the second There were cases where the metal wiring was disconnected. Furthermore, the difference in level caused by the unevenness of the surface of the glabellar insulating film also becomes steep, and the second wiring metal may be disconnected at this portion, or conversely, a short circuit may occur between adjacent wirings.

そこで本発明はこのような課題を解決するもので、その
目的とするところは、コンタクトホールの中に導電体を
充填し、この部分における配線の断線を防止するととも
に、眉間絶縁膜表面を平坦化し眉間絶縁膜表面の凹凸に
起因する配線の断線及び短絡を防止する半導体装置の製
造方法を提供するところにある。
The present invention is intended to solve these problems, and its purpose is to fill the contact hole with a conductor to prevent the wiring from breaking in this area, and to flatten the surface of the insulating film between the eyebrows. An object of the present invention is to provide a method for manufacturing a semiconductor device that prevents disconnections and short circuits in wiring caused by unevenness on the surface of an insulating film between the eyebrows.

[課題を解決するための手段] 本発明は、半導体基板上方の第1の絶縁膜上に形成され
た第1の配線上に、前記第1の配線を構成する材質とは
異なる材質より成る導電膜を形成する工程。
[Means for Solving the Problems] The present invention provides a conductive wire made of a material different from the material constituting the first wire, on a first wire formed on a first insulating film above a semiconductor substrate. The process of forming a film.

フォト・エツチングによりコンタクトホールとなるよう
に設計された部分に前記導電膜より成る突起を形成する
工程。
A step of forming a protrusion made of the conductive film in a portion designed to become a contact hole by photo-etching.

前記第1の配線及び前記導電膜より成る突起を含む前記
第1の絶縁膜上の全面に第2の絶縁膜を形成する工程。
forming a second insulating film over the entire surface of the first insulating film including the first wiring and the protrusion made of the conductive film;

前記の第2の絶縁膜上に、その表面が平坦になるように
、凸部分では厚く、凹部分では薄く被膜を形成する工程
A step of forming a film on the second insulating film so that its surface is flat, thicker in the convex portions and thinner in the concave portions.

前記被膜及び前記第2の絶縁膜を互いに等しいエツチン
グ速度でエツチングし、前記導電膜より成る突起を露出
させる工程。
Etching the coating film and the second insulating film at the same etching rate to expose protrusions made of the conductive film.

前記導電膜より成る突起を介して前記第1の配線と電気
的に接続されるように第2の配線を形成する工程。
forming a second wiring so as to be electrically connected to the first wiring via the protrusion made of the conductive film;

よりなることを特徴とする。It is characterized by being more.

[実施例] 本発明の実施例における工程断面図を、第1図(a)〜
(f)に示し、以下工程順に詳細に説明していく。
[Example] Process cross-sectional views in Examples of the present invention are shown in Figures 1(a) to 1(a).
It is shown in (f) and will be explained in detail below in order of steps.

まず最初に、第1図(a)のように、半導体基板101
上方に形成されたアルミニウム・シリコン合金膜103
よりなる第1の配線を含む酸化珪素膜102上に全面的
にタングステン膜104を形成する。このとき、アルミ
ニウム・シリコン合金膜の膜厚は8000人、タングス
テン膜の膜厚は8000人である。
First, as shown in FIG. 1(a), a semiconductor substrate 101
Aluminum-silicon alloy film 103 formed above
A tungsten film 104 is formed entirely on the silicon oxide film 102 including the first wiring. At this time, the thickness of the aluminum-silicon alloy film is 8000 mm, and the thickness of the tungsten film is 8000 mm.

次に、第1図(b)のように、フォト・エツチングによ
り、第2の配線と導通をとる部分、すなわち、コンタク
トホールとなる部分にのみタングステン膜104を残し
、それ以外のタングステン膜104は除去する。このと
き、エツチングはドライエツチングによって行なってお
り、その条件は、  CF4=50secm、  6P
a、  500Wで。
Next, as shown in FIG. 1(b), by photo-etching, the tungsten film 104 is left only in the part that conducts with the second wiring, that is, in the part that will become the contact hole, and the other tungsten film 104 is Remove. At this time, etching was performed by dry etching, and the conditions were as follows: CF4 = 50 sec, 6P
a. At 500W.

この条件下では、タングステンは容易にエツチングされ
るが、下層のアルミニウム・シリコン合金j′1103
及び酸化珪素膜102はエツチングされない。
Under these conditions, tungsten is easily etched, but the underlying aluminum-silicon alloy j'1103
And the silicon oxide film 102 is not etched.

次に、第1図(C)のように2層間絶縁膜として、化学
的気相成長法により酸化珪素膜105を7000人形成
する。
Next, as shown in FIG. 1C, a silicon oxide film 105 is formed by 7000 layers as an interlayer insulating film by chemical vapor deposition.

次に、第1図(d)のように、酸化珪素膜1゜5上にフ
ォトレジスト106を回転塗布する。このとき、フォト
レジストは凸部分には薄く、凹部分には厚く形成される
ため、その表面は平坦になっている。
Next, as shown in FIG. 1(d), a photoresist 106 is spin-coated on the silicon oxide film 1.5. At this time, the photoresist is formed thinly on the convex portions and thickly on the concave portions, so that the surface thereof is flat.

次に、第1図(e)のように、フォトレジスト106と
酸化珪素膜105のエツチング速度が等しくなるような
エツチング条件で、フォトレジスト106及び酸化珪素
l11105を連続的にエツチングし、タングステン膜
104上の酸化珪素膜105が完全に除去されタングス
テン膜104が露出するまでるまでエツチングする。こ
のときのエツチング条件は、CF4=30SCCm、0
2:20 s e c m、  6 P a、  80
0 Wであった。
Next, as shown in FIG. 1(e), the photoresist 106 and the silicon oxide film 11105 are continuously etched under etching conditions such that the etching rates of the photoresist 106 and the silicon oxide film 105 are equal, and the tungsten film 104 is etched continuously. Etching is performed until the upper silicon oxide film 105 is completely removed and the tungsten film 104 is exposed. The etching conditions at this time are CF4=30SCCm, 0
2:20 sec m, 6 P a, 80
It was 0W.

最後に、第1図(f)のように、アルミニウム・シリコ
ン合金106よりなる第2の配線を形成し、第1の配線
と第2の配線は電気的に接続される。
Finally, as shown in FIG. 1(f), a second wiring made of aluminum-silicon alloy 106 is formed, and the first wiring and second wiring are electrically connected.

[発明の効果] 以上述べたように1本発明によれば、第1の配線上のコ
ンタクトホールとなるように設計された部分に、第1の
配線とは異なる材質より成る導電膜の突起を形成した後
に、眉間絶縁膜を形成し。
[Effects of the Invention] As described above, according to the present invention, a protrusion of a conductive film made of a material different from that of the first wiring is formed in a portion of the first wiring designed to be a contact hole. After this, an insulating film between the eyebrows is formed.

エッチバック法を用いて表面を平坦化するとともに、突
起を露出させた後、この上に第2の配線を形成し、この
突起を介して第1の配線と第2の配線を電気的に導通さ
せるようにすることにより。
After flattening the surface using an etch-back method and exposing the protrusion, a second wiring is formed on this, and the first wiring and the second wiring are electrically connected through this protrusion. By letting them.

第1の配線と第2の配線の接続部分における断線。Disconnection at the connection between the first wiring and the second wiring.

及び層間絶縁膜表面の急峻な凹凸に起因する第2の配線
の断線、短絡を防止できるという効果を有し、これによ
り高歩留りで高信頼性の半導体装置を造ることができる
ようになった。
It also has the effect of preventing disconnections and short circuits in the second wiring caused by steep irregularities on the surface of the interlayer insulating film, and as a result, it has become possible to manufacture highly reliable semiconductor devices with high yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(f)は2本発明の半導体装置の製造方
法を示す工程断面図。 第2図(a)〜(c)は、従来の半導体装置の製造方法
を示す工程断面図。 101.201 102、 202 103、 203 104゜ 105、 204 106゜ 107、 205 半導体基板 酸化珪素膜(絶縁膜) アルミニウム・シリコン 合金(第1の配線) タングステン 酸化珪素膜(層間絶縁膜) フォトレジスト アルミニウム・シリコン 合金(第2の配線) o3 10う Oy
FIGS. 1(a) to 1(f) are process cross-sectional views showing two methods of manufacturing a semiconductor device according to the present invention. FIGS. 2(a) to 2(c) are process cross-sectional views showing a conventional method for manufacturing a semiconductor device. 101.201 102, 202 103, 203 104°105, 204 106°107, 205 Semiconductor substrate silicon oxide film (insulating film) Aluminum-silicon alloy (first wiring) Tungsten silicon oxide film (interlayer insulating film) Photoresist aluminum・Silicon alloy (second wiring) o3 10oy

Claims (1)

【特許請求の範囲】 半導体基板上方の第1の絶縁膜上に形成された第1の配
線上に、前記第1の配線を構成する材質とは異なる材質
より成る導電膜を形成する工程、フォト・エッチングに
よりコンタクトホールとなるように設計された部分に前
記導電膜より成る突起を形成する工程、 前記第1の配線及び前記導電膜より成る突起を含む前記
第1の絶縁膜上の全面に第2の絶縁膜を形成する工程、 前記の第2の絶縁膜上に、その表面が平坦になるように
、凸部分では厚く、凹部分では薄く被膜を形成する工程
、 前記被膜及び前記第2の絶縁膜を互いに等しいエッチン
グ速度でエッチングし、前記導電膜より成る突起を露出
させる工程、 前記導電膜より成る突起を介して前記第1の配線と電気
的に接続されるように第2の配線を形成する工程、 よりなることを特徴とする半導体装置の製造方法。
[Claims] A step of forming a conductive film made of a material different from a material constituting the first wiring on a first wiring formed on a first insulating film above a semiconductor substrate; - forming a protrusion made of the conductive film in a portion designed to become a contact hole by etching; a step of forming a second insulating film on the second insulating film, a step of forming a film thickly on the convex parts and thinly on the concave parts so that the surface thereof is flat; etching the insulating films at the same etching rate to expose the protrusions made of the conductive film; forming a second wiring so as to be electrically connected to the first wiring via the protrusions made of the conductive film; A method for manufacturing a semiconductor device, comprising: a step of forming it.
JP19913088A 1988-08-10 1988-08-10 Manufacture of semiconductor device Pending JPH0247852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19913088A JPH0247852A (en) 1988-08-10 1988-08-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19913088A JPH0247852A (en) 1988-08-10 1988-08-10 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0247852A true JPH0247852A (en) 1990-02-16

Family

ID=16402639

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19913088A Pending JPH0247852A (en) 1988-08-10 1988-08-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0247852A (en)

Similar Documents

Publication Publication Date Title
US4789648A (en) Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
US6051882A (en) Subtractive dual damascene semiconductor device
US4470874A (en) Planarization of multi-level interconnected metallization system
US6103629A (en) Self-aligned interconnect using high selectivity metal pillars and a via exclusion mask
JPH0360055A (en) Manufacturing method of integrated circuit
US6384481B1 (en) Single step electroplating process for interconnect via fill and metal line patterning
JPH01503021A (en) Flattening method for forming through conductors in silicon wafers
KR100455380B1 (en) Semiconductor device having multilevel interconnections and method for manufacturing the same
US6355554B1 (en) Methods of forming filled interconnections in microelectronic devices
JP2561602B2 (en) Method for manufacturing contact of multi-layer metal wiring structure
JPH0247852A (en) Manufacture of semiconductor device
JPH03148130A (en) Manufacture of semiconductor device
KR100352304B1 (en) Semiconductor device and method of manufacturing the same
JP2783898B2 (en) Method for manufacturing semiconductor device
KR100226755B1 (en) Metal wiring structure and manufacturing method of semiconductor device
JPH05226475A (en) Method for manufacturing semiconductor device
JPS61239646A (en) Formation of multilayer interconnection
KR920001913B1 (en) Semiconductor manufacturing method using pattern layer
JPS6297353A (en) Mutual connection of planar metal for vlsi device
JPS63107043A (en) Forming method of conductive line for semiconductor device
JPH0462855A (en) Semiconductor device and manufacture thereof
KR960007642B1 (en) Manufacturing method of semiconductor device
JPH05160126A (en) Formation of multilayer wiring
JPH11214513A (en) Wiring structure of integrated circuit, and wiring formation method
JPH03239348A (en) Semiconductor device and its manufacture