JPH0247875A - Semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the breakdown of gate insulating films and the decline of element life by a method wherein floating gate transistors are inserted into the electric source input line or high voltage input line of a MOS transistor and connected to the MOS transistor as load elements. CONSTITUTION:In a semiconductor device containing an N-type channel MOS transistor Tn and double-layer polycrystalline silicon gate structure floating gate transistors Tfd and Tfg, the source of the MOS transistor Tn is connected to a grounding terminal, its drain is connected to a Vd electric source node through the first floating gate transistor Tfd and its gate is connected to an input node through the second floating gate transistor Tfg. The control gates of the floating gate transistors Tfd and Tfg and the drains of the floating gate transistors Tfd and Tfg are connected to each other respectively. With this constitution, the reliability defect such as the breakdown of the gate insulating films and the decline of the element life can be avoided.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device including an insulated gate type element (MOS element), and particularly relates to a power supply path or a high voltage input path for a MOS transistor. Regarding.

(Prior Art) Conventionally, as for power input to a MOS transistor in a semiconductor device including a MOS element, basically, as shown in FIG.
Drain 32 and gate 30 of OS transistor Tn
The power supply voltage Vd is directly input to the terminal. On the other hand, in order to meet the recent demands for higher integration and higher performance of semiconductor devices, it has become essential to reduce the element dimensions and to make the gate insulating film 31 thinner.

However, the external power supply voltage does not necessarily decrease due to compatibility with conventional products and connection with external equipment. In this case, M
The gate insulating film 31 of the OS transistor is thin, so if the external power supply voltage is input directly to the MOS transistor, a high electric field will be applied to the gate insulating film 31, causing damage to the gate insulating film 31 and shortening of the device life. unreliability occurs. That is, taking an N-channel E type MOS transistor as an example, when Vd is applied to the drain 32 of the MOS transistor, the gate voltage Vg is 0 (v).
At this time, the transistor is turned off, and a voltage of Vg-Vd--Vd is applied to its gate insulating film 31. Further, when 0 (V) is applied to the drain 32 and the gate voltage Vg is Vd, the transistor is turned off, and a voltage of Vd-Vg-Vd is applied to the gate insulating film 31. Therefore, if the voltage applied to the gate insulating film 31 is greater than a critical value, the gate insulating film 31 will be defective.

To avoid this, countermeasures have been proposed, such as using a power supply voltage drop circuit to step down the power input and supply it to the internal circuit, but the MOS transistor in the first stage of power input is
It is not possible to use a gate insulating film with the same thickness as the S transistor, and it is necessary to form different gate insulating films for the first-stage power input stage element and internal MOS element, which increases costs. There were problems such as causing

In addition, in semiconductor devices that use high voltage, such as nonvolatile memories that have two-layer gate electrodes, high-voltage MOS
It is necessary to form the gate insulating film of the transistor to be thicker than the gate insulating film of the internal MOS transistor, which causes problems such as complicating the process and increasing costs.

(Problems to be Solved by the Invention) As described above, the present invention aims to reduce the thickness of the gate insulating film of a MOS transistor in order to achieve the demands for higher integration and higher performance of semiconductor devices. (MOS)
This was developed to solve the problem that the gate insulating film of transistors and high-voltage MOS transistors needs to be made thicker than the gate insulating film of internal MOS transistors, resulting in increased costs. Even if the gate insulating film of a power input first-stage MOS transistor or high-voltage MOS transistor is formed to have the same thickness as the gate insulating film of an internal MOS transistor, the gate insulating film may be destroyed or the device life may be shortened. An object of the present invention is to provide a semiconductor device that can protect a MOS transistor without causing reliability defects, complicating the process, or increasing costs.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a semiconductor device including a MOS transistor and a floating gate transistor, in which the floating gate transistor is connected to a power input path or a high voltage input path to the MO5) transistor. is inserted and connected as a load element.

(Function) By appropriately setting the capacitance ratios of the capacitance C1 between the substrate and the floating gate, the capacitance 1i1C2 between the floating gate and the control gate, and the capacitance C3 between the floating gate and drain region, most of the The Vd voltage can be dropped to an arbitrary voltage, and this dropped voltage is applied to the MOS transistor. Therefore, even if the gate insulating film of MOS transistors is made thinner in order to meet the demands for higher integration and higher performance of semiconductor devices, reliability problems such as destruction of the gate insulating film of MOS transistors and reduction in device life may occur. No defects will occur.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a part of the circuit of a semiconductor device, such as an EFROM (ultraviolet erasable rewritable read-only memory), including a MOS transistor and a floating gate transistor with a two-layer polycrystalline silicon gate structure, and Tn is N
Channel type M-os transistors, Tfd and Tf
Each of the transistors g is an N-channel floating gate transistor and is configured similarly to an EPROM memory cell.

The source of the MOS transistor Tn is connected to the ground potential terminal, its drain (output node) is connected to the Vd power supply node via the first floating gate transistor Tfd serving as a load element, and its gate is It is connected to the input node via the second floating gate transistor Tfg. The above floating gate transistor Tfd
and Tfg are respective control gates. The drains are connected to each other, and a voltage lowered by the respective gate thresholds is applied to the drain and gate of the MOS transistor Tn.

FIG. 2 shows an example of the structure of the MOS transistor Tn and the floating gate transistor Tfd on its drain side, each of which has a lightly doped drain structure.
A pedDrain (LDD) structure is adopted. That is, 20 is a P-type semiconductor substrate, 21 and 22 are a gate insulating film of the MOS transistor Tn and a gate electrode made of polycrystalline silicon, and 23 and 24 are a high concentration N+ impurity region and a low concentration for the drain of the MOS transistor Tn. N- impurity regions 25 and 26 are the MO
A high concentration N+ impurity region and a low concentration N− impurity region for the source of the S transistor Tn, and a low concentration N+ impurity region inside the high concentration N medium impurity region 23.25 (on the channel region side of the MOS transistor Tn). N-'' impurity region 2
4.26.

On the other hand, 27 and 28 are floating gate transistors Tf
d, the first gate insulating film and the second gate insulating film 29 and 30 are the first gate insulating film and the second gate insulating film 29 and 30 of the floating gate transistor Tfd.
The gate electrode (floating gate made of polycrystalline silicon) and the second gate electrode (control gate made of polycrystalline silicon), 31 and 32, are the floating gate transistor T.
33 and 34 are a high concentration N medium impurity region and a low concentration N'' impurity region for the source of the floating gate transistor Tfd. A low concentration N- impurity region 32.34 is formed inside the high concentration N medium impurity region 31.33 (on the channel region side of the floating gate transistor Tfd).

The high concentration N medium impurity region 23 for the drain of the MOS transistor Tn and the high concentration N medium impurity region 33 for the source of the floating gate transistor Tfd are formed in series.

Note that the control gate electrode 30 of the floating gate transistor Tfd may have a stacked structure of silicide and polycrystalline silicon. Furthermore, the gate insulating film 21 of the MOS1-transistor Tn and the first gate insulating film 21 of the floating gate transistor Tfd are
A silicon oxide film is used as the gate insulating film 27, and the second gate insulating film 28 of the floating gate transistor Tfd includes only a silicon oxide film or a laminated structure of a silicon oxide film and a silicon nitride film. can be used.

Now, V is applied to the drain of the floating gate transistor Tfd.
d is applied, when the voltage Vcg of the control gate electrode 30 is 0 (V), the transistor T
fd is turned off, and Vf is applied to the first gate insulating film 27.
A voltage of g-Vd is applied. Here, Vfg is the voltage of the floating gate electrode 29 of the transistor Tfd, and is determined by the capacitance ratio as shown in the following equation. That is, the capacitance between the substrate 20 and the floating gate electrode 29 of the transistor Tfd is 01, the capacitance between the floating gate electrode 29 and the control gate electrode 30 is 02, and the capacitance between the floating gate electrode 29 and the drain region is 01. 03 and C1+C2+C3-Ct, it becomes Vf g-(C2/Ct)Vcg+(C3/Ct)Vd. At this time, since Vcg-0 (V), Vf
g-Vd-(C3/Ct-1)Vd--! (C1+C2
)/Ct) Vd<Vd, and the voltage applied to the first gate insulating film 27 is less than Vd.

Also, 0 is applied to the drain of the floating gate transistor Tfd.
(V), the control gate electrode 30
When the voltage Vcg is Vd, the transistor Tfd is turned off, and a voltage of Vd-Vfg = [(C1+C2)/Ctl Vd<Vd is applied to the first gate insulating film 27, which is more relaxed than Vd. will be done.

Note that the above-mentioned state exists when no charge is accumulated in the floating gate electrode 29, but by increasing the gate length of the floating gate transistor Tfd and making the drain junction have an LDD structure, the floating gate Injection of charge into the electrode 29 can be completely prevented.

As mentioned above, by inserting and connecting a floating gate transistor as a load element of a MOS transistor,
A voltage lowered by the gate threshold of the floating gate transistor is applied to the drain and gate of the MOS transistor.

In this case, by appropriately setting the capacitance ratio of the floating gate transistor as shown in the old method, the Vd voltage can be lowered to almost any desired voltage.

Therefore, in order to achieve the demands for higher integration and higher performance of semiconductor devices, it is necessary to
When increasing
S) Even if the gate insulating film is formed to have the same thickness as the gate insulating film of the transistor, reliability defects such as destruction of the gate insulating film and reduction in device life will not occur.

Moreover, as mentioned above, floating gate transistors can be
A structure in which an OS transistor is inserted and connected as a load element can be easily formed in a semiconductor device having two or more layers of gate electrodes, without complicating the process or increasing costs.

Note that although the above embodiment shows an EFROM, other semiconductor devices (such as SRAM and D
The present invention can also be applied to RAM (RAM, etc.). Furthermore, the present invention is applicable not only to N-channel type MOS elements as in the above embodiments but also to P-channel type MOS elements.

[Effects of the Invention] As described above, according to the semiconductor device of the present invention, MO3
) When making the gate insulating film of a transistor thinner, the gate insulating film of the MO3) transistor in the first stage of a power supply or high voltage system MOS) transistor should be formed to have the same thickness as the gate insulating film of the internal MO3) transistor. Also, reliability defects such as destruction of the gate insulating film and reduction in device life do not occur, and the MOS transistor can be protected without complicating the process or increasing costs.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a part of the semiconductor device of the present invention, and FIG. 2 shows an example of the structure of the MO, S transistor in FIG. 1 and the floating gate transistor on the drain side thereof. 3(a) is a circuit diagram showing a MOS transistor at the first stage of power input in a conventional semiconductor device, and FIG. 3(b) is a sectional view showing the structure of the MO3) transistor in FIG. 3(a). . T n-----・-MOS transistor, Tfd, T
fg...Floating gate transistor, 20...
... P-type semiconductor substrate, 21 ... gate insulating film, 22 ... gate electrode, 23 ... high concentration N medium impurity region for drain, 24.・・・・・・
Low concentration N- impurity region for drain, 25...
・High concentration N+ impurity region for source, 26...
・Low concentration N'' impurity region for source, 27...
...First gate insulating film, 28... Second gate insulating film, 29... First gate electrode (floating gate electrode), 30... Second gate electrode ( control gate electrode), 31...High concentration N+ impurity region for drain, 32...Low concentration N- impurity region for drain, 33...... High concentration N- impurity region for drain. High concentration N medium impurity region, 34...Low concentration N'''' for source
Impurity region, C1, C2, C3...capacitance. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] A semiconductor device including a MOS transistor and a floating gate transistor, characterized in that the floating gate transistor is inserted and connected as a load element to a power input path or a high voltage input path to the MOS transistor. semiconductor devices.