JPH0247909A - Reference voltage generating circuti - Google Patents
Reference voltage generating circutiInfo
- Publication number
- JPH0247909A JPH0247909A JP19831288A JP19831288A JPH0247909A JP H0247909 A JPH0247909 A JP H0247909A JP 19831288 A JP19831288 A JP 19831288A JP 19831288 A JP19831288 A JP 19831288A JP H0247909 A JPH0247909 A JP H0247909A
- Authority
- JP
- Japan
- Prior art keywords
- resistors
- selection
- circuit
- resistor
- selection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
- Attenuators (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は基準電圧の発生回路、特に1抵抗分割によって
基準電圧を発生する基準電圧の発生回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reference voltage generation circuit, and more particularly to a reference voltage generation circuit that generates a reference voltage by dividing one resistor.
従来、この種の基準電圧の発生回路では、必要とする分
解能の分だけの数の抵抗器を直列に接続し、その抵抗器
で分圧した電圧を選択的に出力していた。Conventionally, in this type of reference voltage generation circuit, a number of resistors corresponding to the required resolution are connected in series, and a voltage divided by the resistors is selectively output.
ここでは、電源電圧(以降VDDという)の1/16ず
ツノ分解能で0/16×vDDがらIV16XVDDま
での基準電圧を得る回路を例にとって説明する。Here, a circuit for obtaining a reference voltage from 0/16×vDD to IV16×VDD with a 1/16-point resolution of the power supply voltage (hereinafter referred to as VDD) will be explained as an example.
第6図は従来の基準′電圧発生回路のフ゛ロック図で、
16個の抵抗器R101〜R116を直列に接続し電源
電圧を16分割している。選択回路10は16分割した
電位のうちの1つを選択してアナログ出力Voを出力す
る・電圧の選択は選択信号SO〜S3で行い、その選択
の論理F1a1g7図に示す通シで、選択信号SO〜S
3がnの場合fl/16VDI)のタップを選択する。Figure 6 is a block diagram of a conventional reference voltage generation circuit.
Sixteen resistors R101 to R116 are connected in series to divide the power supply voltage into 16 parts. The selection circuit 10 selects one of the 16 divided potentials and outputs the analog output Vo.The selection of the voltage is performed using the selection signals SO to S3, and the selection signal is determined according to the logic of the selection F1a1g7 as shown in the figure. SO~S
If 3 is n, select fl/16VDI) tap.
上述した従来の基*電圧の発生回路は、必要な分解能の
数だけの抵抗器を用意しなければならなかった。また、
選択回路も必要な分解能の数だけの人力を選択しなけれ
ばならず、回路規模が大きくなっていた。In the conventional base*voltage generation circuit described above, it was necessary to prepare as many resistors as the required resolution. Also,
The selection circuit also had to be manually selected for the number of resolutions required, resulting in an increase in circuit scale.
このためこのような基準電圧発生回路をIC化する場合
において1jIcのテア1面積が増大してコストアップ
するという欠点があった。本発明の目的は、抵抗器での
分圧を2回行うことによって、抵抗器の数と選択回路の
回路規模を小さくする基準電圧の発生回路を提供するこ
とにある。For this reason, when such a reference voltage generation circuit is implemented as an IC, there is a drawback that the tear 1 area of 1jIc increases, leading to an increase in cost. An object of the present invention is to provide a reference voltage generation circuit that reduces the number of resistors and the circuit scale of the selection circuit by performing voltage division using resistors twice.
本発明の基準電圧発生回路は、n個の抵抗器81〜ルn
を直列接続し一端を1源に接続し他端を接地し電源電圧
を分圧する第1の抵抗列と、m個の抵抗器R11〜ル1
mを直列接続した第2の抵抗列と、前記第2の抵抗列を
前記抵抗器Rk(k暑1〜n)の両端に選択的に並列接
続する接続手段と、前記第2の抵抗列で分圧した電圧を
選択して基準電圧を出力する選択手段と、前記第1の抵
抗列のうちの抵抗器ルに以外の抵抗器に前記第2の抵抗
列の直列抵抗直に相当する値のn−1個の補正抵抗器を
それぞれ選択的に並列接続する補正手段とを含んで構成
される。The reference voltage generation circuit of the present invention includes n resistors 81 to n.
A first resistor string is connected in series with one end connected to one source and the other end is grounded to divide the power supply voltage, and m resistors R11 to R1.
a second resistor string connected in series, a connecting means for selectively connecting the second resistor string in parallel to both ends of the resistor Rk (k heat 1 to n); selection means for selecting a divided voltage and outputting a reference voltage; and a selection means for selecting a divided voltage and outputting a reference voltage; and a correction means for selectively connecting n-1 correction resistors in parallel.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
gt図は本発明の一実施例のプロ、り図である。The gt diagram is a professional diagram of one embodiment of the present invention.
抵抗器3l−R4ti直列接続されており、一端は電源
電位に、他端を接地電位にある。The resistors 3l-R4ti are connected in series, one end being at power supply potential and the other end being at ground potential.
電源と抵抗器ル1との接続点をA点(電位は4/ 4
VDD )
抵抗器ル1と抵抗器ル2との接続点をB点(電位は3
/ 4 vDD )
抵抗器凡2と抵抗器R3との接続点を0点(電位は2
/ 4 VDD )
抵抗器凡3と抵抗器具4との接続点をD点(電位は1/
4VDD)
抵抗器ル4と接地との接続点をE点と呼ぶ。The connection point between the power supply and resistor 1 is point A (potential is 4/4
VDD) Connect the connection point between resistor 1 and resistor 2 to point B (potential is 3
/ 4 vDD) Connect the connection point between resistor 2 and resistor R3 to 0 point (potential is 2
/ 4 VDD) Connect the connection point between resistor 3 and resistance device 4 to point D (potential is 1/4 VDD).
4VDD) The connection point between resistor 4 and ground is called point E.
選択回路1はA点からDJまでの電位を人力として、選
択信号S2及び83で1電位を選択して出力する◎第2
図はその選択論理を示す・選択回路2FiB点からE点
までの電位を入力として選択信号S2及びS3で11を
位を選択して出力する選択回路である。′isz図はこ
の選択論理を示す0抵抗器kLtt−R14は直列接続
されておシ、一端は選択回路lの出力に、他端は選択回
路2の出力に接続されている〇
選択回路1と抵抗器ル11との接続点をF点、抵抗器a
llと抵抗器凡12との接続点を0点、抵抗器R12と
抵抗器313との接続点をH点、抵抗器具13と抵抗器
ル14との接続点を1点、抵抗器具14と選択回路2と
の接続点を1点と呼ぶ。The selection circuit 1 uses the potential from point A to DJ as human power, and selects and outputs one potential using selection signals S2 and 83. ◎Second
The figure shows the selection logic. Selection circuit 2 This is a selection circuit that inputs the potential from point FiB to point E, selects the 11th place using selection signals S2 and S3, and outputs the selected result. 'isz diagram shows this selection logic.0 resistors kLtt-R14 are connected in series, one end is connected to the output of selection circuit 1, and the other end is connected to the output of selection circuit 2. The connection point with resistor 11 is point F, and resistor a
Select the connection point between ll and resistor 12 as 0 point, the connection point between resistor R12 and resistor 313 as point H, the connection point between resistance device 13 and resistor L 14 as 1 point, and select resistance device 14. The connection point with circuit 2 is called one point.
選択回路3はF点から1点までの電位を入力として選択
信号SO及び81で1電位を選択してアナログ出力電圧
vOを出力する。第3図はその選択論理を示す。The selection circuit 3 inputs potentials from point F to one point, selects one potential using selection signals SO and 81, and outputs an analog output voltage vO. FIG. 3 shows the selection logic.
第5図は、11択qfi号80〜8375!100IB
(2進表記)のときの選択の様子を例として示している
。。Figure 5 shows 11 choices qfi number 80~8375!100IB
(binary notation) is shown as an example. .
選択回路IFiB点(12/16Von)を、選択回路
ZHC点(8/ 16 VDD ) ヲ’14択f ル
(Dテ、F点〜J点はその電位を4等分し、それぞれ1
2/ 16 VDD 〜8/ 16 Vnts トuル
。M択回M3dI点を選択するため、出力電圧Fi9/
l 6 VDDとなる。The selection circuit IFiB point (12/16Von) is changed to the selection circuit ZHC point (8/16VDD).
2/16 VDD ~ 8/16 Vnts tor. In order to select the M selection M3dI point, the output voltage Fi9/
l 6 VDD.
ここで、抵抗器凡11〜R14を抵抗器ル2に並列接続
したことによって実際には分圧が多少くずれる。従りて
B点の電位は12/ l 6 V!IDよ如多少低く0
点の電位ti 8 / 16 VDDよシ多少高くなっ
てしまう。Here, by connecting the resistors 11 to R14 in parallel to the resistor 2, the partial voltage actually collapses to some extent. Therefore, the potential at point B is 12/l 6 V! ID is somewhat low 0
The potential at the point ti 8 / 16 is somewhat higher than VDD.
抵抗器321〜R24Fiこの分圧を正しく4/16
VnBずりにする補正用の抵抗器で、スイ、テ8W1〜
SW4をオンすると、それぞれ抵抗器B1〜R4に並列
に接続する。抵抗量比21〜R24の抵抗値は、抵抗器
R11〜R14の直列抵抗に等しい1直とする。Resistor 321~R24Fi Correctly adjust this voltage to 4/16
This is a resistor for correcting VnB deviation.Sui, Te8W1~
When SW4 is turned on, it is connected in parallel to resistors B1 to R4, respectively. The resistance values of the resistance ratios 21 to R24 are 1 series, which is equal to the series resistance of the resistors R11 to R14.
スイッチ8W1−8W4の制御は選択信号S2及びS3
で行い、その制御論理は第4図に示す。The switches 8W1-8W4 are controlled by selection signals S2 and S3.
The control logic is shown in FIG.
第5図に示す場合は、スイッチ8W1とSW3とsw4
をオンし、スイッチSW2をオフすることによっテ、B
点d 12/ 16 VnnK、C点ハ8/ 16 V
!Inに補正できる。従って1点は9/16VDDにな
シ、正確なアナログ出力電圧を得ることができる。In the case shown in FIG. 5, switches 8W1, SW3 and sw4
By turning on the switch SW2 and turning off the switch SW2, the
Point d 12/16 VnnK, point C 8/16 V
! It can be corrected to In. Therefore, one point can be 9/16 VDD and an accurate analog output voltage can be obtained.
このように、本発明によれば、たとえば16段階の電圧
を得るために必要な抵抗の数は補正用を含めて12個で
あり、従来の16個の75esで実現することができる
。As described above, according to the present invention, the number of resistors required to obtain, for example, 16 levels of voltage is 12 including those for correction, which can be realized using the conventional 16 75ES resistors.
また、電圧の選択回路も、16人力のものが必要であっ
たが4人力の選択回路が3個とスイッチ4個で実現する
ことができる。Furthermore, although the voltage selection circuit required 16 manpower, it can be realized with three four-manpower selection circuits and four switches.
ここでは16段階の例を示したが、たとえば8ビ、ト精
度すなわち256段階の電圧を得る場合においては、従
来Fi256個の抵抗器が必要だったのに対して、本発
明によればわずか5分の1足らずの48個の抵抗器で実
現できるため大幅に回路規模を削減できる。Although an example of 16 stages is shown here, for example, in order to obtain a voltage with 8-bit accuracy, that is, 256 stages, 256 Fi resistors were conventionally required, but according to the present invention, only 5 resistors are required. Since it can be realized with 48 resistors, which is less than one-fold, the circuit scale can be significantly reduced.
以上説明したように、本発明は、抵抗による分圧を2回
行い、それにより生じる誤差を補正する手段を有するこ
とによシ、ごく少い回路で基準電圧を発生させることが
できる。このため、この回路をIC化した場合には、安
いコストでICを供給で色るという効果がある。As explained above, the present invention can generate a reference voltage with a very small number of circuits by performing voltage division twice using resistors and having a means for correcting errors caused by the voltage division. Therefore, when this circuit is integrated into an IC, there is an effect that the IC can be supplied at a low cost.
第1図は本発明一実施例のプロ、り図、第2図。
第3図、第4図は第1図の制御論理を示す説明図、第5
図Fi第1図の動作原理を示す回路図、第6図は従来の
一例のプロ、り図、第7図t[6図の制御論理を示す説
明図である。
1.2.3・・・・・・選択回路、10・・・・・・選
択回路、几l〜凡4.几11〜R14.R21〜R24
゜几101〜R116・・・・・・抵抗器、8W1〜S
W4・・・・・・スイッチ、Sθ〜83・・・・・・選
択信号、Vo・・・・・・アナログ出力。
代理人 弁理士 内 原 晋
第1図
第2図
第3図
第4図
第5図
第6圓FIG. 1 is a professional diagram of an embodiment of the present invention, and FIG. Figures 3 and 4 are explanatory diagrams showing the control logic of Figure 1;
Fig. 1 is a circuit diagram showing the operating principle of Fig. 1, Fig. 6 is an explanatory diagram showing the control logic of an example of the conventional system. 1.2.3... Selection circuit, 10... Selection circuit, 几l~ 4.几11~R14. R21-R24
゜几101~R116・・・Resistor, 8W1~S
W4...Switch, Sθ~83...Selection signal, Vo...Analog output. Agent Patent Attorney Susumu Uchihara Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6
Claims (1)
し他端を接地し電源電圧を分圧する第1の抵抗列と、m
コの抵抗器R11〜R1mを直列接続した第2の抵抗列
と、前記第2の抵抗列を前記抵抗器Rk(k=1〜n)
の両端に選択的に並列接続する接続手段と、前記第2の
抵抗列で分圧した電圧を選択して基準電圧を出力する選
択手段と、前記第1の抵抗列のうちの抵抗器Rk以外の
抵抗器に前記第2の抵抗列の直列抵抗値に相当する値の
n−1個の補正抵抗器をそれぞれ選択的に並列接続する
補正手段とを含むことを特徴とする基準電圧の発生回路
。m
a second resistor string in which resistors R11 to R1m are connected in series; and the second resistor string is connected to the resistor Rk (k=1 to n).
connecting means selectively connected in parallel to both ends of the resistor Rk; selection means selecting the voltage divided by the second resistor string and outputting a reference voltage; and a resistor other than Rk in the first resistor string. and a correction means for selectively connecting in parallel n-1 correction resistors each having a value corresponding to the series resistance value of the second resistor string to each of the resistors. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19831288A JPH0247909A (en) | 1988-08-08 | 1988-08-08 | Reference voltage generating circuti |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19831288A JPH0247909A (en) | 1988-08-08 | 1988-08-08 | Reference voltage generating circuti |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0247909A true JPH0247909A (en) | 1990-02-16 |
Family
ID=16389033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19831288A Pending JPH0247909A (en) | 1988-08-08 | 1988-08-08 | Reference voltage generating circuti |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0247909A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0575466A (en) * | 1991-09-17 | 1993-03-26 | Nec Ic Microcomput Syst Ltd | Resistor voltage divider |
| US5363070A (en) * | 1992-12-09 | 1994-11-08 | Mitsubishi Denki Kabushiki Kaisha | Attenuator having phase between input and output signals independent of attenuation |
| JP2007019801A (en) * | 2005-07-07 | 2007-01-25 | Oki Electric Ind Co Ltd | Digital/analog converter |
| JP2017022594A (en) * | 2015-07-13 | 2017-01-26 | アズビル株式会社 | Photoelectronic sensor |
-
1988
- 1988-08-08 JP JP19831288A patent/JPH0247909A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0575466A (en) * | 1991-09-17 | 1993-03-26 | Nec Ic Microcomput Syst Ltd | Resistor voltage divider |
| US5363070A (en) * | 1992-12-09 | 1994-11-08 | Mitsubishi Denki Kabushiki Kaisha | Attenuator having phase between input and output signals independent of attenuation |
| JP2007019801A (en) * | 2005-07-07 | 2007-01-25 | Oki Electric Ind Co Ltd | Digital/analog converter |
| JP2017022594A (en) * | 2015-07-13 | 2017-01-26 | アズビル株式会社 | Photoelectronic sensor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4338591A (en) | High resolution digital-to-analog converter | |
| US4491825A (en) | High resolution digital-to-analog converter | |
| US4573005A (en) | Current source arrangement having a precision current-mirror circuit | |
| JPH06314977A (en) | Current output type d/a converter circuit | |
| JP3130528B2 (en) | Digital to analog converter | |
| JPH0239136B2 (en) | ||
| JP2009005051A (en) | DA conversion circuit | |
| JPH0377430A (en) | D/a converter | |
| JPH0247909A (en) | Reference voltage generating circuti | |
| JP2837726B2 (en) | Digital to analog converter | |
| KR20020034832A (en) | Digital/analog conversion apparatus | |
| US7295142B2 (en) | Digital-to-analog converter with short integration time constant | |
| JP2005252663A (en) | Current cell matrix type digital/analog converter | |
| JP4746792B2 (en) | A / D converter | |
| JP4625739B2 (en) | Resistor voltage division type digital / analog conversion circuit | |
| US4814740A (en) | Glitch occurence prevention circuit for a digital/analog converter | |
| JPH09116438A (en) | Digital / analog converter | |
| JP3877747B1 (en) | A / D converter | |
| JP3360298B2 (en) | D / A converter | |
| JP2778286B2 (en) | D / A converter circuit | |
| US5684483A (en) | Floating point digital to analog converter | |
| EP0177909A2 (en) | Digital-to-analog converter | |
| JPS62265809A (en) | Reference voltage generating circuit | |
| JPS63246927A (en) | Reference voltage generating circuit | |
| JP2976447B2 (en) | D / A converter |