JPH0247924A - Frequency dividing circuit - Google Patents

Abstract

PURPOSE:To realize a frequency dividing circuit operated up to a considerable rate of a high frequency by adopting an emitter follower stage for the constitution of current storage transistors(TRs) and improving the current gain. CONSTITUTION:The state of current storage TRs Q5, Q6 of an FF is changed at the leading of an input pulse fed to a terminal 1, and the state of current storage TRs Q1, Q3 and Q2, Q4 of an FF is changed at the leading of the same input pulse. Thus, an output pulse being the result of 1/2 frequency division of a voltage generated across load resistors R7, R9 by a current from current storage TRs Q5, Q7 and Q6, Q8 of the FF is outputted from terminals 5, 6. Driving TRs of each FF and reference TRs (Q17 and Q19, Q18 and Q20) are replaced at the trailing of an input pulse capable of extraction of a frequency division output from the FF similarly. Thus, an emitter follower is adopted for the constitution of the current storage TRs to form a frequency divider capable of operation up to 70% of the high frequency or over.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frequency divider circuit, and particularly to a master-slave type frequency divider circuit used for dividing high frequencies such as microwave bands.

[Conventional technology]

As a logical frequency divider circuit that can obtain stable operation up to high frequencies, two sets of R-
A master-slave type frequency divider circuit shown in FIG. 3 in which 8-T type flip-flops are differentially combined with each other is known. This circuit consists of transistors Ql, Q2. QI, Q*,
Qe Q2° and resistance R1, R! , Rs.
Rs, Rs-Rl 2, and connected as shown. 1 is an input terminal, 2 and 3 are current source terminals, 5,
6 is an output terminal.

Conventionally, semiconductor integrated circuits using this type of frequency dividing circuit have been reported up to about 10 GHz at the research stage, but the upper limit frequency remains at about 60% of the high cutoff frequency (fT) of transistor elements.

[Problem to be solved by the invention]

In the above-mentioned branching device, as the high cutoff frequency approaches, the current storage transistors Ql, Q2 .
The current waveform is distorted due to a decrease in the current gain of Qa and Qa or a decrease in the current holding function, resulting in unstable operation. In order to compensate for this, there is a method of increasing the operating current of the current storage transistor, but it is difficult to optimize the increase or distribution of the circuit current, including the transistor operating current before and after the current storage transistor.

[Means to solve the problem]

The frequency dividing circuit of the present invention includes two current storage transistors connected as emitter followers, and a 21'i feedback transistor connected to the base of one of these current storage transistors and the emitter of the other to form a positive feedback circuit. and two switching transistors that are connected to the bases of the current storage transistors and transmit binary inputs, respectively, and are differentially coupled to each other.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. Ql and Q3
, Q2 and Q4 and Q, and Q7, Q, and Q, are the first transistors of the first and second flip-flops, respectively.
and second, third and fourth, fifth and sixth, seventh and eighth current storage transistors, R1 to R, are connected to the emitters of current storage transistors Q and ~Q#, and These are the first to eighth load resistors that constitute the emitter follower circuit. Transistors Q0 to Q1□ have their bases connected to current storage second stage transistors Qs, Q4 . Q7. Qs
It is a feedback transistor that is connected to the emitter of Ql! and forms a positive feedback circuit with resistors R and ~R12, and is connected to the emitter of transistor Ql! ~Q1. The collectors of these transistors are connected to the bases of the first stage transistors Q, , Q, , Qs, and Qs for current storage, respectively, and transmit the binary input to set (S) and reset (S) and reset ( R) A switching transistor that constitutes an input.

The emitters of the second-stage current storage transistors Q s , Q < of the first flip-flop are the switching transistors Q 1s , Q of the second flip-flop, respectively.
2 for current storage of the second flip-flop at the base of B.
The emitters of the stage transistors Q t and Q s are respectively the transistors Q1 for switching the flip-flops.
41 Connected to the base of Qn.

Feedback transistors Q and Q of the first flip-flop
l. , and the emitters of the switching transistors QH and Q+s of the second flip-flop are connected to constant current source terminals 2 and 3 via drive transistors q+y and Qzo to which input pulses (clock pulses) are applied from terminal 1, respectively.
, the feedback transistor Q of the second flip-flop
++ r Q H and the first flip-flop switching transistor Q1. .

The emitter of Ql4 is connected to the reference voltage (v8
) are connected to constant current source terminals 3 and 2 via reference transistors Q1s and Ql9, to which are added.

The rising edge of the input pulse applied to terminal 1 changes the states of the current storage transistors Q, Q6 of the second flip-flop, and the falling edge of the same input pulse changes the state of the current storage transistors Q1, . Q3 and Q2
．． Q changes the state of current storage transistors Q s , Q r and Q a of the second flip-flop.
, Qs The voltage generated across the load resistors Ra and Rs by the currents is output from terminals 5 and 6 as an output pulse whose frequency is divided by two. Note that a positive voltage v0° is applied to the power supply terminal 7.

Regarding the falling edge of the input pulse, the driving transistor of each flip-flop and the reference transistor (Ql, and Q
By interchanging n r Q ra and Q2°), it is possible to similarly obtain the effect of extracting the branch output from the second flip-flop.

FIG. 2 shows the current waveforms flowing through the load resistors R9 and R1° in FIG. and a current waveform representing the sum of the collector currents of Q and s. If the operating frequency is low enough, the current flowing through load resistor R9, Q connected to R1, and Ql
The sum of the collector current and the collector current is equal to -, and stable operation can be obtained. On the other hand, as the operating frequency becomes higher, a difference occurs in the current waveforms as shown in FIG. This difference current represents the current flowing into and flowing into current storage transistors Q1 and Q2.

FIG. 4 shows current waveforms at the same frequency when the conventional circuit shown in FIG. 3 is used. In the conventional circuit in which the current storage transistor is composed of a single Emifluoro stage, there is a large difference between the current flowing through the load resistor R9 and the sum of the collector currents of Q and Ql3 connected to R1, and the branching operation becomes unstable over time. It has become.

FIG. 5 is a circuit diagram of another embodiment of the present invention.

The circuit configuration is the same as that in FIG. 2, but the collector terminals of the current storage transistors Q1 to Q are separated from other circuit connections and connected to a positive power supply v0° and another positive power supply v0°'. Power supply V. . is normally set to +5v, but vo. ′
For example, even if the voltage is set to 6V, the circuit current hardly increases.

By increasing the voltage, the current storage transistor Q
Since the base input capacitance of 1 to Q is reduced, there is an advantage that branching operation at high frequencies becomes advantageous.

〔Effect of the invention〕

As explained above, the frequency divider circuit of the present invention has an improved current gain by using a two-stage Emifluoro structure for the current storage transistor. This has the effect of being realized as a frequency dividing circuit that can operate up to a frequency of 100% or more.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2 is an operating current waveform diagram when Figure 1 is used, Figure 3 is a conventional circuit diagram, and Figure 4 corresponds to Figure 3. FIG. 5 is a circuit diagram of another embodiment of the present invention. Q, -Ql... Current storage transistor, Q,
~q+s...Switching transistor, Q,,,Q
! .・・・・・・Drive transistor, Qll# Ql
m...Reference transistor, R1-R1...
...Load resistance, R0~R1! ······resistance. Agent: Patent Attorney Susumu Uchihara'J) @cki4J2Toto, Be

Claims (1)

[Claims] two current storage transistors with emitter-follower connection; two feedback transistors connected to the base of one of these current storage transistors and the emitter of the other to form a positive feedback circuit; and each of the current storage transistors. first and second flip-flops each having two switching transistors connected to the base and transmitting a binary input are differentially coupled to each other, and the current storage transistor is connected to a two-stage emitter follower. A frequency divider circuit characterized in that it is composed of transistors.