JPH0247925A - Clock signal generator - Google Patents

Abstract

PURPOSE:To avoid simultaneous operation stop of both systems or malfunction by arranging a selector to an input side of a phase synchronizing type oscillator and providing a cross path through which an output of an oscillator of other system to the oscillator via a selector of its own system. CONSTITUTION:A selector 10 and an oscillator 20 are provided on the 0 system in a clock signal generator and a selector 11 and an oscillator 21 are provided on the 1 system respectively. The selectors 10, 11 have two input terminals 0, 1 respectively, and either of the terminals 0, 1 is connected to an output terminal. When the oscillator 20 is faulty and stops its operation, the reception of a clock signal from the oscillator 20 via the selector 11 is interrupted to the oscillator 21 and a self-running clock signal is being sent by its own oscillation output. When a controller detects the fault and the selection of the selector 10, 11 is switched from the terminal 0 into the input terminal 1, a clock signal from a host equipment is received via a selector 11 and the oscillator 21 outputs and sends a signal synchronously with the received clock signal as the signal of the 1 system.

Description

[Detailed Description of the Invention] 22 [Industrial Application Field] A clock signal generator that sends out two systems of clock signals by duplicating phase synchronized oscillators in which the generated clock signal is synchronized with the clock signal received from the outside. Regarding.

[Conventional technology]

Conventional clock signal generators of this type are constructed by connecting two built-in phase-locked oscillators (hereinafter referred to as oscillators) with a clock signal from a host device, and connecting two selectors to the output sides of the two oscillators. , the two selectors select the output of one of the two oscillators and output it to the outside.

FIG. 2 shows the countries constituting the block, showing an example of the conventional system. Second
As shown in the figure, the two systems O system and 1 system each have oscillators 80 and 81 and a selector 9.
Each of the 0 oscillators 80 and 81 having 0 and 91 inputs a clock signal received from the 0 system and 1 system from the host device, respectively, and connects a clock signal synchronized with this signal to both the selectors 9o and 91. Selectors 90 and 91 select one of the two inputs and output it. Selector 90/9
The oscillator 80 for the 0 system and the oscillator 81 for the 1 system are input to the 1, and the selectors 90 and 91 select either the 0 system or the 1 system when instructed from the outside. Normally, the selectors 90 and 91 select and send out the output of the oscillator 80 with the system currently in use, and if the 0 system is in trouble,
Switch and connect to the spare 1 system.

[Problem to be solved by the invention]

In the conventional clock signal generation device described above, when the output of the active oscillator is cut off, the output cutoff is detected as a failure, and the clock signal is supplied to both devices until the selector is instructed to select input to the standby side. This has the disadvantage of causing both systems to stop working or malfunction.

SUMMARY OF THE INVENTION An object of the present invention is to provide a clock signal generation device that eliminates the above drawbacks by providing a selector on the input side and an oscillator on the output side.

[Means to solve the problem]

The clock signal generation device of the present invention is a clock signal generation device that sends out two systems of clock signals by duplicating phase synchronized oscillators in which the generated clock signal is synchronized with a crack signal received from the outside. A clock signal received from the phase-locked oscillator, an external device, and a clock signal output from the phase-locked oscillator of another system are respectively input, and one of the two systems receives the clock signal from the external device, and the other system receives the clock signal from the other system. and a selector that selects a clock signal from each of the phase-locked oscillators, connects the clock signal to the phase-locked oscillator of the same system, and alternates the selection according to an instruction from the outside.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, the clock signal generating device has a selector 10 and an oscillator 20 in a 0-system system, and a selector 11 and an oscillator 21 in a 1-system system.

Each of the selectors 10 and 11 has two input terminals 0 and 1.
and connect one of input terminals 0 and 1 to the output terminal according to the instructions. The output terminals of selectors 10 and 11 are connected to oscillators 20 and 21, respectively.

The selector 10 of the 0-system system connects the clock signal from the host device to input terminal 0, and connects the oscillator 21 to input terminal 1.
Connect the output of A clock signal from a host device is connected to the input terminal 1 of the selector 11 of the 1-system system, and an output of the oscillator 20 is connected to the input terminal O. Oscillator 20.2
1. Each clock signal output is sent to the selector 11 of the other system.
・Connect to input terminals 0 and 1 of each of 10, and
Sent as external output.

Each of the selectors 10 and 11 connects the input terminal O to the output terminal by using the O system in normal operation, and connects the input terminal O to the output terminal when the 0 system, for example, the oscillator 20, has a failure.
Switch to the system and connect input terminal 0 to output terminal.

Therefore, in current use, the oscillator 20 externally transmits a clock signal synchronized with a clock signal received from a host device (not shown) via the selector 10. The oscillator 21 receives the clock signal transmitted by the oscillator 20 and outputs the synchronized clock signal from the 1-system system.

When the oscillator 20 fails and does not stop operating, the oscillator 2
1 is interrupted from receiving the clock signal from the oscillator 20 via the selector 11, but continues to send out the free-running clock signal as its own oscillation output.

A control device (not shown) detects a fault and selector 10
- When the selection of 11 is switched from input terminal 0 to input terminal 1, the clock signal from the host device is received via the selector 11, and the oscillator 21 outputs a signal synchronized with the received clock signal as a 1-system system.・Can be sent.

〔Effect of the invention〕

As explained above, the present invention provides a selector on the input side of a phase-locked oscillator, and provides a confounding path for inputting the output of another system's oscillator to the oscillator via its own system's selector. Even if the output of the system oscillator is cut off, the clock signal output will not be interrupted due to the free-running clock signal of the standby system oscillator, and both systems will have a highly reliable device that will not stop operating or malfunction. There are configurable effects.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a clock signal sending device of the present invention;
FIG. 2 is a configuration diagram showing a conventional example. 10.11... Selector, 30.21... Oscillator.

Claims (1)

[Claims] In a clock signal generation device that sends out two systems of clock signals by duplicating a phase synchronized oscillator whose generated clock signal is synchronized with a crack signal received from the outside, each of the two systems includes the phase synchronized oscillator and an external device. The clock signal received from the oscillator and the clock signal output from the phase-locked oscillator of the other system are respectively input, and one of the two systems receives the clock signal from the external device, and the other receives the clock signal from the phase-locked oscillator of the other system. 1. A clock signal generating device comprising: a selector which selects and connects each of the phase synchronized oscillators to phase synchronized oscillators of the same system, and alternates the selection according to an instruction from an external device.