JPH0247929A - decoder circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a decoder circuit composed of eight CMO circuits, and particularly relates to an improvement in decoding ability.

2. Description of the Related Art An example of a conventional decoder circuit composed of eight CMO circuits is shown in FIG. In Figure 2, 1 is a power supply voltage terminal, 2
is a ground terminal, 11 to 42 are P-type MOS transistors, 5
1 to 82 are N-type MOS transistors, AO-A3 and A
O%A3 is an address control signal input terminal, yt-ys is a decode signal output terminal, and 3 is a NOR type decoder unit circuit.

Next, the operation of the decoder circuit described above is performed for the NOR type decoder unit circuit 3. Each P, N type transistor, 11
The same address control signal is input to , 51.12, 52.13, 53.14, and 54, respectively. If all four types of address control signals are now logic 0, that is, if the P-type MO8 transistors 11 to 14 are conductive (hereinafter, this state will be referred to as the main selection state), the Ni2MO8) transistor 51
54 becomes non-conductive, and a logic 1 signal is output to the decode signal output terminal Y+. Next, if one of the four types of address control signals is at logic 1, at least one of the P-type MoS transistors 11 to 14 becomes non-conductive (this state is defined as a non-selected state). At least one of the N-type MOS transistors 51 to 54 becomes conductive, and a logic O signal is output to the decode signal output terminal Yl.

Therefore, depending on the value of the address control signal, the decode output can be selected as either logic O or logic 1.

Problems to be Solved by the Invention However, in the above configuration, a large number of transistor elements are required to configure the decoder circuit. In the example shown in Figure 2, 64
It requires several transistors. Therefore, since the number of elements is large, there is a big restriction on high integration of the circuit.

In view of these problems, it is an object of the present invention to reduce the number of elements, realize a highly integrated circuit, and provide a decoder circuit with improved arithmetic performance.

Means for Solving the Problems The present invention provides a decoder circuit using a CMOS inverter circuit, wherein the source terminals of the first and second inverter circuits are connected to the drain terminal of a third inverter circuit, and the third and second inverter circuits are connected to each other. The source terminal of the fourth inverter circuit is connected to the drain terminal of the fifth inverter circuit, the source terminals of the fifth and sixth inverter circuits, and the drain terminal of the seventh inverter circuit. This decoder circuit is characterized in that one of the complementary transistors is selected by an address control signal to generate a decode signal.

It is possible to realize a decoder circuit that reduces the number of active components, increases the circuit integration, reduces current consumption, and improves functionality.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows one embodiment of the present invention, and FIG.
The same parts as in the conventional example in the figure are indicated by the same numbers. 1 is a power supply voltage terminal, 2 is a ground terminal, 11 to 25 are P-type MOS transistors, 51 to 65 are N-type MoS transistors, Ao-A
3, A, -A3 are address control signal input terminals, Y1~
Y8 is a decode signal output terminal.

The operation of the decoder circuit configured as described above will be explained below. First, address control signal A
When all four outputs of O-A3 are logic O (hereinafter, this state is referred to as a selected state), P-type MOS transistors 11 to 14
becomes conductive, and N-type MOS transistors 51 to 54 become non-conductive. Therefore, the current path is the P-type MOS transistor 11
14, and a logic 1 signal is output to the decoder signal output terminal Y+. Next, address control signal AO~
If A2 is logic O and only A3 is logic 1, then P type M
OS transistors 11 to 13 are conductive, 14 is non-conductive, N
MOS transistors 51 to 53 are non-conductive, MOS transistor 54 is conductive, and a logic 0 signal is output to the decoder signal output terminal Y1. Note that in this input state, the address l
Since a logic 0 signal is input to the 1lII signal input terminal T3, the P-type MOS transistor 15 becomes conductive and the N-type MOS transistor 15 becomes conductive.
The S transistor 55 becomes non-conductive, and a logic 1 signal is output from the decoder signal output terminal Y2. Next, when only address control signal A2 is logic 1, P-type MOS transistors 11, 12.14 are conductive, 13.15 is non-conductive, N-type MoS transistor 51.52 is non-conductive, and 53.55 is non-conductive. It becomes conductive. At this time, P-type MOS transistors 14, 15, N-type MOS transistors 54.55
A logic O signal is input to the source terminal of , and a logic O signal is output from both decoder signal output terminals Y1 and Y2.

The same theory as above can be applied to A I + A O, and a decoder circuit that outputs a decoder signal of logic 1 when in the selected state and logic O otherwise can be constructed.

As described above, according to this embodiment, it is possible to reduce the number of constituent elements, increase the degree of integration, and at the same time realize a decoder circuit that reduces the overall conductor length required for input signals. I can do it.

Effects of the Invention In the present invention, a 4-bit decoder circuit is composed of 60 transistors, whereas in the conventional example shown in FIG. 2, 128 transistors are required. In this way, high integration can be achieved with a small number of elements, and at the same time, the overall length of conductive wire required for input signals can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a decoder circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of an example of a conventional decoder circuit. 1...Power supply voltage terminal, 2...Ground terminal, 3...NOR type decoder unit circuit, 11-4
2...P-type MOS transistor, 51-82.
...N-type MOS transistor, Ao~A3e
A O~A3...Address control signal input terminal, Yl~Y8...Decode signal output terminal.

Claims (1)

[Claims] A decoder circuit using a CMOS inverter circuit, wherein source terminals of the first and second inverter circuits are connected to a drain terminal of a third inverter circuit, and source terminals of the third and fourth inverter circuits are connected to a fifth inverter circuit. The drain terminal of the inverter circuit is connected to the source terminal of the fifth and sixth inverter circuits, and the drain terminal of the seventh inverter circuit, and one of the complementary transistors is connected by an address control signal input to each inverter. A decoder circuit that selects a decoder and generates a decode signal.