JPH0248741A - Testing system for microcomputer - Google Patents

Abstract

PURPOSE:To map the address of the peripheral circuit of a custom microcomputer in accordance with the request of a customer, and to make the regeneration of a necessary test pattern for every product unnecessary by changing the address mapping of the peripheral circuit for usual working time and testing time. CONSTITUTION:When a test mode is designated from an external part through a test signal input terminal 110, a test signal generation circuit 107 is connected to a data input/output terminal 108 through control signal lines 112 to 114 by a control signal 112, and the data bus 102 is connected to the data input/output terminal 108 through a switching circuit 111. At that time, a CPU is isolated from the peripheral circuits 105, 106, and is mapped in the address designated by decode circuits 117, 121, and becomes capable of being accessed from the external part through an address input terminal 109 and the data input/output terminal 108. Thus, such a defect that the test pattern needs to be corrected when the mapping of the address of each peripheral circuit is different for every customer can be eliminated.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a testing method for microconbeaters.

[Conventional technology]

A conventional microcomputer testing method will be explained with reference to the drawings. FIG. 3 is a configuration diagram of a conventional microcomputer test method, in which 101 is a CPU, 102 is a data bus, 105 and 106 are peripheral circuits, 107 is a test signal generation circuit, 108 is a second plurality of terminals, and 109 is a 3 multiple terminals, 110 the first multiple terminals, 111 the first switching circuit, 112 the test control signal, 201 the second
202 is an address bus, 2α, 3 is a test control signal, 301.303 is a decoding circuit, 30
2,303 is a decode signal.

When a signal specifying the normal operating state is input through the input terminal 110, the test signal generation circuit 107 uses the test control signals 112 and 203 to transfer the data bus 102 to the CPU 101 via the first switching circuit 111 and the address bus 2.
02 to CPU10L via the second switching circuit 201.
Connect to.

Therefore, the CPU can address the peripheral circuits 105 and 106 mapped to the addresses designated by the decoders 301 and 303.

Next, when a signal specifying a peripheral circuit isolation test is input from the input terminal 110, the test signal generation circuit 107 uses the test control signals 112 and 203 to transfer the data bus 102 to the input/output terminal 108 via the first switching circuit 111. , the address bus 202 is connected to the input terminal 109 via the second switching circuit 201 . Therefore, the peripheral circuit 10
5 and 106 are arranged so that data can be input/output via the terminal 108 in accordance with the address input from the terminal 109.

As explained above, in the conventional test method, according to the address mapping of multiple peripheral circuits, the address of the peripheral circuit specified by the CPU during normal operation and the address specified to the peripheral circuit by the external pin during testing are the same. It became.

[Problem to be solved by the invention]

The conventional microcomputer test method mentioned above is
Since the addresses of peripheral circuits are the same during normal operation and during testing, microcomputers (hereinafter referred to as custom microcontrollers) are designed to integrate any number of peripheral circuits on a single chip at any address specified by the customer. omitted)
In K, test programs and test patterns necessary for testing the operation of each peripheral circuit are stored in a pre-created library unique to each peripheral circuit. However, since the above test pattern includes address information for each peripheral circuit, if the address mapping of each peripheral circuit differs depending on the customer, it is necessary to modify the test pattern. The disadvantage is that the address mapping of the peripheral circuits must be fixed.

[Means to solve the problem]

The microconbeater test method of the present invention includes a test signal generation circuit that generates a test control signal for distinguishing between a normal operating state and a plurality of test states based on signals applied to a first plurality of terminals; The test control signal controls the data bus from the CPU during normal operation to the second test during the first test.
a switching circuit connected to multiple terminals of the CPU, a first address bus to which address signals of peripheral circuits are output from the CPU, a second address bus to which an external address is input during testing, and A plurality of first decoded signals receiving the bus and the test control signal and outputting the first decoded signal.
a plurality of second decode circuits that receive the second address bus and the test control signal and output a second decode signal; the first decode signal and the second decode signal; It is characterized by having a plurality of peripheral circuits that are addressed by and input/output data via a data bus.

It has an address bus that is input to the first decoder circuit and the plurality of second decoder circuits, and the address bus is connected to the CPU during normal operation by the pattern test control signal, and the third decoder circuit is input to the third decoder circuit during the first test. It is also possible to have a configuration including a switching circuit connected to a plurality of terminals.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic diagram of an embodiment of the present invention.

CPU10I executes programs, processes data, and controls peripheral circuits. The data bus 102 is a bus for inputting/outputting data of peripheral circuits, and is connected to the CPU10I during normal operation and to the data input/output terminal 108 during testing according to a test control signal 112. The address bus 103 conveys address information from the CPU 10I to the decoder 115.

119 input. Address input terminal 109 is an address input terminal from the outside during testing, and address bus 10
It becomes an input to decoders 117 and 121 via 4. The peripheral circuit 105 receives a control signal 113 and a decode signal 116,1.
18 are selected and input and output data to and from the data bus 102. The peripheral circuit 106 receives a control signal 114 and a decode signal 12o.

122 and inputs and outputs data to and from the data bus 102. The test signal generation circuit 107 receives an external test mode designation signal through an input terminal 110 and generates test control signals 112 to 114.

Next, the operation of this embodiment will be explained.

During normal operation, the test signal generation circuit is the test signal input terminal 1.
10 specifies normal operation via control signal lines 112 to 114. At this time, the control signal 112 causes the data bus 102 to switch to G via the switching circuit 111.
Connected to PUIOI.

Peripheral circuits 105 and 106 are instructed by control signals 113 and 114 to enable block code signals 116 and 120 and to disable decode signals 118 and 122. Therefore, during normal operation, CPUl0I is decoded by decoding circuits 115 and 119.
Peripheral circuit 105 mapped to the address specified by
．． 106, the input/output terminal 108 and the input terminal 109 and the peripheral circuit 105
, 106 becomes impossible.

Next, when a test mode is specified from the outside via the test signal input terminal 110, the test signal generation circuit 107 specifies the test mode via the control signal lines 112 to 114. In the case of input/output, the control signal 112 connects the data bus 102 to the data input/output terminal 108 via the switching circuit 111. Peripheral circuits 105 and 106 receive decoded signals 116 and 120 using control signals 113 and 114.
is specified to be invalid and the decode signals 118 and 122 are valid. Therefore, during testing, the CPU is peripheral circuit 10.
5, 106, peripheral circuits 105, 106 are mapped to addresses specified by decoding circuits 117, 121, and address input terminals 109. It becomes possible to access from the outside via the data input/output terminal 10B.

FIG. 2 is a block diagram of a second embodiment of the invention. C
PUl0I executes programs, processes data, and controls peripheral circuits. A data bus 102 is a bus for inputting and outputting data of peripheral circuits, and is connected to the CPU 101 during normal operation and to the data input/output terminal 108 during testing according to a test control signal 112. Address bus 202 is connected to C during normal operation by test control signal 203.
During testing, it is connected to the address input terminal 109 via the switching circuit 201 to transmit address information from the CPU or the outside to the decoding circuits 115, 117, 1.
The input is 19,121.

The peripheral circuit 105 receives a control signal 113 and a decode signal 116.
．． 118 and inputs and outputs data to and from the data bus 102. Peripheral circuit 106 is selected by control signal 114 and decode signals 120 and 122 and connected to data bus 10.
2 and data input/output. Test signal generation circuit 10
7 is an input terminal 110 for inputting a test mode designation signal from the outside.
Test control signals 112, 113, 11 are input via
4°203 is generated.

Next, the operation of this embodiment will be explained.

During normal operation, the test signal generation circuit connects control signal lines 112 to
114 and 203 to specify normal operation. At this time, the control signal 112 connects the data bus 102 to the CPUIOI via the switching circuit 111, and the control signal 203 connects the address bus 202 to the CPUIOI via the switching circuit 201. Peripheral circuits 105 and 106 are designated by control signals 113 and 114 to enable decode signals 116 and 120 and to disable decode signals 118 and 122. Therefore, during normal operation, the CPU 101 uses the peripheral circuits 105 and 106 mapped to the addresses specified by the decoding circuits 115 and 119.
Input/output terminal 1
Peripheral circuits 105 and 106 from 0B and input terminal 109
access becomes impossible.

Next, when the external test mode is specified via the test signal input terminal 110, the test signal generation circuit 107 specifies the test mode via the control signal lines 112 to 114 and 203. At this time, the control signal 112 connects the data bus 102 to the data input/output terminal 108 via the switching circuit 111, and the control signal 203 connects the address path 202 to the address input terminal 109 via the switching circuit 201. Peripheral circuit 105°10
6 is a block code signal 116 by control signals 113 and 114.
, 120 are made invalid and the decoded signals 118, 122 are made valid. Therefore, during testing, the CPU cannot access the peripheral circuits 105 and 106;
．． 106 is mapped to the address specified by the decoding circuits 117 and 121 and is input to the address input terminal 109. External access is now possible via the data input/output terminal 108.

This embodiment has the advantage that it requires less layout area than the first embodiment because only one address bus is required.

〔Effect of the invention〕

As explained above, the present invention is designed to change the address pin pink of peripheral circuits during normal operation and during testing.
In a custom microcontroller, the addresses of peripheral circuits can be mapped according to the customer's wishes, and during testing, they can be mapped to addresses specific to each peripheral circuit, so there is no need to recreate the test patterns needed for each product when testing a product. There is an effect.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a first embodiment of the present invention. FIG. 2 is a schematic diagram of a second embodiment of the present invention. FIG. 3 is a diagram of a conventional microcomputer testing method. 101...CPU, 102...-data bus, 103...first address bus, 104
...Second address bus, 105, 106...
... Peripheral circuit, 107 ... Test signal generation circuit, 108 ... Data input/output terminal, 109.
... Address input terminal, 110 ... Test signal input terminal, 111 ... Switching circuit, 1
12, 113, 114...-Test control signal line, 115, 119...First decoding circuit, 1
17, 121... Second decoding circuit, 116
．． 120...First addressing signal, 118
．． 122...Second addressing signal, 201
...Second switching circuit, 202...
Address bus, 2o3...Test control signal line, 301°303...Decode circuit, 302,
303...Decode signal line. Figure 2 Figure 3

Claims (2)

[Claims] (1) A test signal generation circuit that generates a test control signal that distinguishes between a normal operating state and a plurality of test states based on signals applied to a first plurality of terminals, and a a switching circuit that connects to the CPU in a normal operating state and to a second plurality of terminals in a first test state of the plurality of test states;
a first address bus to which an address signal is output; a second address bus to which a second address signal is input from a third plurality of terminals in the first test state; a plurality of first decoding circuits that decode the test control signal and generate a first addressing signal; and a plurality of first decode circuits that decode the second address signal and the test control signal and generate a second addressing signal. A test of a microcomputer comprising a plurality of second decoding circuits and a plurality of peripheral circuits selected by the first and second addressing signals and inputting and outputting data to and from the data bus. method. (2) A test signal generation circuit that generates a test control signal that distinguishes between a normal operating state and a plurality of test states based on signals applied to the first plurality of terminals, and a a first switching circuit connected to the CPU in a normal operating state and to a second plurality of terminals in a first test state of the plurality of test states; an address bus; a second switching circuit that selects a second address signal from a third plurality of terminals and outputs the address signal to the address bus in the first test state; a plurality of first decoding circuits that decode the control signal and generate a first addressing signal; and a plurality of first decoding circuits that decode the second address signal and the test control signal and generate a second addressing signal. 1. A microcomputer testing system comprising: a second decoding circuit; and a plurality of peripheral circuits selected by the first and second addressing signals and inputting/outputting data to/from the data bus.