JPH0248743A - Method and device for address-compare processing - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding an address compare processing method and device that performs a process of trapping to another subprogram when an address compare is obtained during execution of a main program, even after an address comparison is obtained, the subprogram is In parallel with processing, for the purpose of continuing the execution of the main program without interruption, while the processor is executing the main program, the address of the main sequencer for accessing the main program is compared with a preset compare address. An address compare processing method that traps a specified address of a subprogram when a subprogram is detected is to provide a subsequencer that sequentially generates addresses for accessing subprograms, access subprograms after the trapped address, and is configured such that even after the address comparison is completed, the main sequencer continues to access the main program and continues execution of the main program without interruption.

[Industrial application field]

The present invention relates to an address comparison processing method that performs a process of trapping to an address of another subprogram when an address is compared with a preset compare address while a main program is being accessed and executed by a main sequencer. The present invention relates to an address compare processing device suitable for implementation.

[Conventional technology]

In address compare processing, when a program is executed using a sequencer that sequentially sets addresses, and when that address matches a preset compare address, the address is trapped at the address specified at that point and a predetermined processing is performed.

FIG. 4 is a block diagram showing the configuration of a conventional address compare processing device. As processing during address comparison, processing is performed to trace the contents of the trap destination subprogram.

In FIG. 4, a processor 30 includes a sequencer (hereinafter referred to as SQR) 31 that sequentially generates addresses for accessing the main program and subprograms.

A main memory 32 stores the main program executed by the processor 30.

A submemory 33 stores a subprogram to be executed after the address comparison is completed.

40 is an address compare circuit (hereinafter referred to as ADCMP40), and a compare address register 41 (hereinafter referred to as CAR4) stores a compare address to be conveyed inside.
1) and performs address comparison between 5QR31 and CAR41.

In this configuration, the processor 30 sequentially accesses the main program in the main memory 32 using the address generated by 5QR31 and executes the main program sequentially.

On the other hand, the ADCMP 40 conveys the address generated by 5QR 31 and the address of CAR 41, and when the address is compared, that is, when a match is detected between the two, it notifies the processor 40 of this and also sends it to the sub-memory 3.
Trap to a prespecified address of the subprogram in 3.

The processor 30 interrupts the processing of the main program when the address comparison is completed, that is, performs an address compare stop, and also accesses the submemory 33 at the address where 5QR31 occurs, and executes the subprogram after the trapped address. Performs reading and tracing processing.

As a result, after the address comparison is completed, the subprogram after the trapped address is 5QR3.
1 and its contents are traced.

[Problem to be solved by the invention]

In the conventional address compare processing method, the processor
The main program is processed using these SQRs, and after the address comparison is completed, the main program processing is interrupted (
address compare and stop), and the same SQR was used to process the trap destination subprogram.

For this reason, the execution of the main program by the processor after the address comparison is completed is interrupted, resulting in a problem that the processing of the main program is delayed.

The present invention provides an improved address compare processing method that can be performed in parallel with the processing of a trap destination subprogram without interrupting the execution of the main program by the processor even after the address comparison is completed, and its implementation. It is an object of the present invention to provide a suitable address comparison processing device.

[Means to solve the problem]

In order to solve the above-mentioned problems, the means employed in the address compare processing method and apparatus of the present invention will be explained with reference to FIG. FIG. 1 is a block diagram showing the basic configuration of an address compare processing device of the present invention.

In FIG. 1, 10 is a processor, and a main sequencer (
MSQR II) 11 and subsequencer (hereinafter referred to as 5SQR) 12.
When the address of QRII is compared with a preset compare address, processing is performed to access the subprogram after the trapped address using 5SQR12.

Main memory 13 stores a main program executed by processor 10 .

MSQRII generates addresses for accessing the main program in the main memory 13 in order, regardless of whether or not address comparison is achieved.

The submemory 14 stores a subprogram that is executed when address comparison is achieved.

The 5SQR 12 sequentially generates addresses for accessing subprograms in the submemory 14.

Reference numeral 20 denotes an address compare control unit which performs control to trap to a specified address of a subprogram when an address to access the main program is compared with a preset compare address.

Note that the main memory 13 and the submemory 14 may be provided in different areas on a common memory. Further, the subprogram may be part of the main program.

The address compare processing method of the present invention is implemented by the address compare processing device described above, and is configured as follows.

That is, while the processor IO is executing the main program,
In the address comparison processing method, when the address generated by MSQRII, which generates the address to access the main program in order, is compared with a preset compare address, the address is trapped at the specified address of the subprogram. (A) 5SQR12 is provided to sequentially generate addresses for accessing subprograms, and after the address comparison is completed, subprograms after the trapped address are accessed by 5SQRI2; (8) The processor 10: Even after the address comparison is completed, the MSQR 11 continues to access the main program and continues the processing of the main program without interruption.

[For production]

Since the operation of the address compare processing method of the present invention is common to the operation of the address compare processing device of the present invention, the following will be explained below.
The operation of the address comparison processing device of the present invention will be explained according to the processing steps with reference to the address comparison processing flowchart of FIG.

(2) Processing S1 The processor 10 sequentially accesses the main processors in the main memory 13 using the MSQRII and executes the main program.

■ Processing S2 address comparison system? 1lt120c, conveys the address generated by the MSQR11 and a preset compare address, and determines whether the address compare is successful.

(2) Processing S3 When the address comparison is successful, the address comparison control unit 2o performs control to trap the subprogram in the submemory 14 at a prespecified address.

The 5SQR12 sequentially accesses the subprograms after this trapped address. As a result, after the address comparison is completed, the subprogram after the trapped address is accessed by the 5SQR12, and, for example, address tracing is performed.

■ Processing S.

On the other hand, even after the address comparison is completed, the processor 10 continues to access the main program using MSQRII and executes its processing without interruption.

As described above, by providing 5SQR12, the subprogram after the trapped address is accessed after the address comparison is obtained, so even after the address comparison is obtained, the processing of the main program by the processor is trapped. This can be done in parallel with the processing of the previous subprogram.

This allows the processor to continue processing the main program without interruption even after the address comparison is completed, so that delays in main program processing can be completely eliminated.

〔Example〕

An embodiment of the address compare processing method and apparatus of the present invention will be described with reference to FIG. FIG. 3 is an explanatory diagram of the configuration of an embodiment of the address compare processing device of the present invention.

The content of the embodiment of the address compare processing method of the present invention is as follows:
Since the content is common to the explanation of the operation of the address comparison device of the present invention, it will be explained together with the explanation of the operation of the address comparison device.

(A) Configuration of Address Compare Processing Device In FIG. 3, processor 10. MSQRll, 5SQR12,
Main memory 13. The submemory 14 and address compare control section 20 are as described in FIG. 1.

In the address compare control unit 20, 21 is a main address compare circuit (hereinafter referred to as MADCMP), which includes a main compare address register 211 (hereinafter referred to as MCAR211) in which a compare address to be conveyed is set, and the address of MSQRll and MCAR211 are set. When the address comparison of the compare address set in advance is completed, a main trigger signal is generated.

22 is a subaddress compare circuit (hereinafter referred to as SADCMP)
), the sub-compare address register 221 where the compare address to be conveyed is set (hereinafter referred to as 5).
When the address of 5SQR12 and the compare address preset in 5CAR221 are compared, a sub-trigger signal is generated.

MADCMP21 and SADCMP22 have a common configuration.

23 is a main trigger selection circuit (hereinafter referred to as MTSEL), which selects each trigger signal inputted from MADCMP 21 and SADCMP 22, generates a main trap signal for trapping the command address of the main program, and stores the main memory 13 supply to.

24 is a sub-trigger selection circuit (hereinafter referred to as 5TSEL)
Then, each manually inputted trigger signal is selected from the MADCMP 21 and the SADCM P22, and a sub-trap signal for trapping the designated address of the sub-program is generated and supplied to the sub-memory 14.

MTSEL23 and 5TSEL24 have a common configuration.

(B) Operation of the Embodiment As is clear from the structure of the address compare processing device shown in FIG. 3, the main program side and the subprogram side have the same structure. From this, the operation explained next (1
) and (2) are possible. The operation of the address compare processing device shown in FIG. 3, that is, the operation of an embodiment of the address compare processing method of the present invention, will be explained below by dividing into each operation.

(1) Operation (1) In operation (1), MSQR is
When the address comparison of II is successful, it is trapped at the specified address of the subprogram.

In this operation (1), a compare address is set in MCAR211, but no compare address is set in 5CAR221. Therefore, SADCM
No sub-trigger signal is generated from P22.

Moreover, MTSEL23 selects the sub-trigger signal from SADCMP22 or is set to a non-selected state, and 5T
SEL24 is set to select the main trigger signal from MADCMP21.

In this state, the processor 10 sequentially accesses the main programs on the main memory 12 using the MSQRII and executes the main programs.

The MADCMP 21 of the address compare control unit 20
The address of SQRII and the address of MCAR211 are conveyed, and when the address is compared, a main trigger signal is generated.

On the other hand, since no compare address is set in 5CAR 221 of SADCMP 22, address comparison cannot be performed and no sub-trigger signal is generated.

When the main trigger signal is manually input from the MADCMP 21, the 5TSEL 24 generates a sub trap signal and supplies it to the sub memory 14. This traps the prespecified address of the subprogram.

The 5SQR12 sequentially accesses the subprograms after this trapped address. As a result, after the address comparison is completed, the subprogram after the trapped address is accessed by the 5SQR12, and, for example, address tracing is performed.

On the other hand, even when the address comparison is completed, the processor 10 continues to access the main program using MSQRII and executes its processing without interruption.

(2) Operation (2) In operation (2), 5S is executed during the execution of the subprogram.
When the QRII address is compared, it is trapped at the specified address of the main program.

In this operation (2), a compare address is set in 5CAR221, but no compare address is set in MCAR211. Therefore, MADCM
No main trigger signal is generated from P21.

In addition, 5TSEL24 selects the main trigger signal from MADCMP21 or sets it to a non-selected state.
SEL23 is set to select the sub-trigger signal from SADCMP22.

In this state, the processor 10 sequentially accesses the subprograms on the submemory 14 using 5SQRII and executes the subprograms.

The SADCMP 22 of the address compare control 120 is
It conveys the address of 5SQR12 and the address of 5CAR221, and generates a sub-trigger signal when the address is compared.

On the other hand, since no compare address is set in MCAR 211 of MADCMP 21, address comparison cannot be performed and the main trigger signal is not generated.

When the sub-trigger signal is input from the SADCMP 22, the MTSEL 23 generates a main trap signal and stores the main memory 1.
Supply to 3. This traps the prespecified address of the main program.

MSQRII sequentially accesses the main program starting from this trapped address. As a result, after the address comparison is completed, the main program after the trapped address is accessed by the MSQRII, and, for example, address tracing is performed.

On the other hand, even after the address comparison is completed, the processor 10 continues to access the subprogram using the 5SQR 12 and executes its processing without interruption.

As described above, the main program and subprogram can trap each other to the address of the other program on the same basis.

Since it is possible to perform address comparison processing similar to the conventional method described in FIG. 4 using the address comparison processing device shown in FIG. 3, this will be described below as operation (3).

(3) Operation (3) In operation (3), MSQ is
When the RII address comparison is completed, the specified address in the main program is trapped, and the main program after the trapped address is accessed by MSQRlr.

In this operation (3), a compare address is set in MCAR 211. Also, MTSEL23 is M
It is set to select the main trigger signal from ADCMP 21.

In this state, the processor 10 sequentially accesses the main programs on the main memory 12 using the MSQRII and executes the main programs.

The MADCMP 21 of the address compare control unit 20 is
The address of MSQRII and the address of MCAR211 are conveyed, and a main trigger signal is generated when the address is compared.

When the main trigger signal is input from the MADCMP 21, the MTSEL 23 generates a main trap signal and supplies it to the main memory 13. This traps the prespecified address of the main program.

MSQRII sequentially accesses the main program starting from this trapped address. As a result, after the address comparison is completed, the processing of the main program up to that point is interrupted, and the main program after the trapped address is accessed by MSQRll, and, for example, address tracing is performed.

Although the main program side has been described above, address comparison processing can be performed in the same manner on the subprogram side. If done on the subprogram side, use SA
A compare address is set in 5CAR221 of DCMP22, and 5TSEL24 is selected to select the sub-trigger signal generated by SADCMP22.

The contents of the address comparison processing operation on the subprogram side are the same as the address comparison processing operation on the main program side described above, so a description thereof will be omitted.

As described above, according to the address compare processing device of FIG. 3, it is possible to perform conventional address compare processing as well as the address compare processing of the present invention.

〔Effect of the invention〕

As explained above, according to each invention of the present application, the following effects can be obtained.

(1) 5SQR12 is provided so that after the address comparison is obtained, the subprogram after the trapped address is accessed, so even after the address comparison is obtained, the main program processing by the processor is not performed at the trap destination. This can be done in parallel with the subprogram processing.

[2] According to (2) above, the main program processing by the processor continues without interruption even after the address comparison is completed, so that delays in main program processing can be completely eliminated.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the basic configuration of the address compare processing device of the present invention, FIG. 2 is a processing flowchart of the address compare processing method of the present invention, and FIG. 3 is an implementation of the address compare processing device of the present invention. FIG. 4 is an explanatory diagram of the configuration of a conventional address compare processing device. 1 and 3, 10... processor, 11... main sequencer (MS
QR), 12... Subsequencer (SSQR), 13
Main memory, 14... Sub memory, 20... Address compare control L 21... Main address compare circuit (
MADCMP), 211... Main compare address register (MCAR), 22... Sub address compare circuit (SADCMP), 222... Sub compare address register (SCAR), 23... Main trigger selection circuit (MTSEL), 24...Sub trigger selection circuit (STSEL). Basic configuration of the address compare processing device of the present invention FIG. 1 Processing flowchart of the address compare processing method FIG. 2 Configuration of the conventional address compare processing device FIG. 4

Claims (1)

[Claims] 1. While the processor (10) is executing the main program, addresses generated by the main sequencer (11) that sequentially generates addresses for accessing the main program are compared with a preset compare address. In the address compare processing method, which performs the process of trapping to the specified address of the subprogram when the
A subsequencer (12) is provided that sequentially generates addresses for accessing subprograms, and after the address comparison is completed, the subsequencer (12) accesses subprograms after the trapped address, (B) An address comparison processing method, characterized in that the processor (10) continues to access the main program using the main sequencer (11) even after the address comparison is completed, and continues the execution of the main program without interrupting it. 2. A main memory (13) that stores the main program executed by the processor (10), and a submemory (13) that stores the subprogram that is executed when address comparison is achieved.
14) When the processor (10) accesses the main program during execution of the main program and the address is compared with a preset compare address, the processor (10) performs control to trap to the specified address of the subprogram. In an address compare processing device that is equipped with a compare address control unit (20) and performs address compare processing, (A) the address to which the main program in the main memory (13) is sequentially accessed is related to whether or not address comparison has been performed; (B) a main sequencer (11) that sequentially generates addresses for accessing subprograms in the submemory (14);
2) An address compare processing device comprising: