JPH0248813A - Digital filter circuit - Google Patents

Abstract

PURPOSE:To constitute the title circuit of an adding machine with comparatively low speed and a coefficient device by varying the coefficient of the coefficient device and the transfer function of an FIR filter correlatively depending on a delay time required for the calculation of an calculation loop. CONSTITUTION:An output 9/16.Wn is obtained from a coefficient device 13 in response to an output Wn of a data latch and a value Xn in the n-th clock timing of a digital input. The output of a data latch 14 is a 9/16.Wn.Z<-1> and the output of an adder 11 is Xn+9/16.Wn.Z<-1> in the same timing and they are supplied to the latch 12. The calculation loop forms an IIR filter having a transfer function of 1/(1-9/16.Z<-2>). Furthermore, the coefficient device 18, the data latch 19 and the adder 17 form an FIR filter having a transfer function of 1+3/4.Z<-1>, and the data latch 15 and the adding machine 16 form an FIR filter having a transfer function of 1+Z<-1>. Thus, the filter with a transfer function of (1+Z<-1>).(1+3/4.Z<-1>)/(1-9/16.Z<-2>) is formed as a whole.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital filter circuit, and particularly to a digital filter circuit that performs relatively high-speed processing such as video signal processing in real time.

[Conventional technology]

Conventionally, this type of digital filter consists of, for example, an adder that adds inputs from a group of digital input terminals, a data latch that latches the output of this adder, and a coefficient unit that multiplies the output of this data latch by a predetermined coefficient. IIR(
It has a FIR (acyclic) filter that takes the output of this adder or data latch as input, and uses the output of the coefficient unit as the other input of the adder.
The output of the filter was used as a digital filter output.

In Figure 3, the transfer function is (1+Z-”)/(1-3/4・Z
A circuit diagram of an example of a digital filter circuit represented by -1) is shown. The signal from the digital input terminal group 1 is used as one input of the adder 11, the output of this adder 11 is used as the input of the data latch 12, the output of this data latch 12 is used as the input of the coefficient unit 13, and the coefficient The output of the adder 13 is used as the other input of the adder 11, and the data latch 12
The output of the adder 16 is used as the input of the second adder 16 and the data latch 15, the output of the data latch 15 is used as the other input of the adder 16, and the output signal of the adder 16 is used as the output of the digital filter. Note that the coefficient unit 13 outputs a value obtained by multiplying the input by 3/4.

Now, if the value at the n-th clock timing of the digital input signal input from the digital input terminal group 1 is Xfl, and the output of the data latch unit 12 at the same timing is W8, then the coefficient unit 13 inputs Wo and outputs 3. /4
・Output Wll.

In the adder 11, X, and 3/4·W! Enter l, X, +
3/4·Wl is output and input to the data latch unit 12.

Therefore, the output Wail of the data latch circuit 12 at the (n+1)th clock timing is Xfl+3/4−
W, that is, W Q + l = X fi
+3/4 ・W, t, wn = Wfi+,,Z-1, so Wa+t =X-/ (1-3/4- Z-1
), and the output of the data latch 15 at the n-th clock timing becomes W, . . . Z-1. Therefore, the adder 16 calculates W, +W×Z.

In this way, the adder 11, the data latch 12, and the coefficient unit 13 constitute an IIR filter having a transfer characteristic of 1/(1-3/4・Z-1), and the data latch 15
The adder 16 constitutes an FIR filter having a transfer characteristic of 1+Z-1, and the total is (1+2-1)/(
This constitutes a digital filter circuit with a transfer characteristic of 1-3/4.z-1).

[Problem to be solved by the invention]

In the conventional digital filter circuit described above, the IIR filter has an adder that inputs signals from a group of digital input terminals, a data latch that inputs the output of this adder, and a coefficient that inputs this data latch. The output of this coefficient multiplier is used as the other input of the adder, so the calculation of the arithmetic loop consisting of the adder, data latch, and coefficient multiplier can be performed from the digital input terminal group. Sampling period T of input digital input
1, and high speed is required for the adder and coefficient unit.

For example, when processing a digital signal that is sampled at four times the clock frequency of the color subcarrier of an NTSC signal, the processing of both the coefficient multiplier and the adder is 1/4X3.
It needs to be executed during 58MHz = 70ns. This has the drawback of increasing circuit cost and power consumption.

An object of the present invention is to eliminate such drawbacks and improve the transfer characteristics of an IIR filter and an FIR filter by using a coefficient unit and an adder that can be used for a period longer than one sampling period of the calculation digital input of the filter calculation loop. An object of the present invention is to provide a digital filter circuit that can realize desired digital filter characteristics as a whole by changing the transfer characteristics of the filter.

[Means to solve the problem]

The configuration of the digital filter circuit of the present invention includes a cyclic filter consisting of an arithmetic system having at least an adder, a first coefficient multiplier that multiplies a predetermined coefficient, and two or more data latch groups, and a cyclic filter connected in series with the cyclic filter. N stages (
N is an integer greater than or equal to 1)), and the coefficient of the first coefficient unit is KN.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, in which the transfer function is (1
+z-') / (1-3/4-z-') TE shows a digital filter circuit. In this embodiment, a data latch 14.19.20, an adder 17, and one coefficient unit are added to the conventional example. The signal from the digital input terminal group 1 is used as one input of the adder 11,
The output of this adder 11 is input to a data latch 12, the output of this data latch 12 is input to a coefficient unit 13, the output of this coefficient unit 13 is input to a data latch unit 14, and this data latch unit 14 The output of the data latch unit 12 is used as the other input of the adder 11, the output of the data latch unit 12 is input to the second adder 17 and the coefficient unit 18, the output of the coefficient unit 18 is input to the data latch unit 19, and the data The output of one latch is used as the other input of the adder 17,
The output of the adder 17 is used as the input of the data latch 20, the output of this data latch 20 is used as the input of the adder 16 and the data latch 15, and the output of the data latch 15 is used as the other input of the adder 16. , the output of the adder 16 is used as the output of the digital filter.

Here, an adder 11, a data latch 12, and a coefficient unit 13
The delay time required for the calculation of the calculation loop composed of
Therefore, the coefficient of coefficient unit 13 is (3/4) 2 = 9/1
It is set at 6.

Now, let the value of the digital input from digital input terminal group 1 at the n-th tarok timing be Xfi,
The output value of the data latch device 12 at the same timing is W.

Then, the coefficient unit 13 outputs 9/16·Wfi.

The output of the data latch circuit 14 at the same clock timing is 9/16.Wfi.2-1, and the output of the adder 11 is Xl.
Input 9/16, w, ・z-1 and get X, +9/16-
W.

Z-1 is output, and this is used as an input to the data latch unit 12. Therefore, the output Wfi+□ of the data latch device 12 at the (n+1)th clock timing is X, +9
/16・Wfi・z−1. Here, W = W n
By using +1 ・2-1, Wfl+1 =
X, / (1-9/16・Z-2), and the calculation loop consisting of the adder 11, data latch device 12, 14, and coefficient unit 13 has a transfer characteristic of 1/(1-9/16・Z- 2
) constitutes an IIR filter.

Also, at the n-th clock timing, the coefficient unit 1
8 inputs Wfi, data latch 19 inputs 3/4 W
7 ・Outputs Z-1, adder 17 outputs W, +3/4 ・
Wo ・Z-'= (1+ 3/4 ・Z-1) Outputs Wo. Therefore, the coefficient unit 18, the data latch unit 19, and the adder 17 constitute an FIR filter having a transfer characteristic of 1+3/4·Z-1. In addition, the data latch device 15
and adder 16 are FIR filters having the same 1+Z-' transfer characteristic as in the conventional example.

Therefore, as a whole, (1+Z-1)・(1+3/4
- Z-') / (1-9/ 16- Z-2) If we construct a digital filter circuit with the transfer characteristic and simplify this transfer function, we get (1/Z-')/ (1-3
/4・Zl), which is the desired transfer characteristic.

In this case, the processing speed required for the coefficient multiplier 13 and the adder 11 is such that each calculation is performed once within the period T1, and the circuit can be configured with relatively low-speed adders and coefficient multipliers.

FIG. 2 shows that the transfer function of the second embodiment of the present invention is (1+Z−
1)/(1-3/4·Z-1); FIG. In this embodiment, the adder 11. in FIG. The coefficient unit 13 is connected to the adder 40. In addition to the coefficient unit 50, the data latch units 21, 23, 25, 26, 28
,30. Coefficient units 24.29 and adders 22.27 are added. The digital input terminal group 1 is used as one input of the adder 40, and the output of this adder 40 is used as the data latch 1.
2, the output of the data latch 12 is used as the input of the coefficient multiplier 50, the output of the coefficient multiplier 50 is used as the input of the data latch 14, and the output of the data latch 14 is used as the other input of the adder 40. input, and also data latch device 1
2, 21゜26.20 outputs are added to adder 17.2, respectively.
2゜27.16 as one input, and the data latch device 12
．． The outputs of 23.28 and 24.29 are respectively
The outputs of the coefficient multipliers 18 and 24.29 are input to the data latches 19 and 25.30, respectively, and the outputs of the data latches 19 and 25 are respectively input to the data latch 23.
．． 28, and the data latches 19, 25, 30 .
The outputs of 15 are used as the other inputs of adders 17, 22, 27.16, respectively, and the outputs of adders 17, 22.27 are used as inputs of data latches 21, 26.20, respectively.
The output of the data latch 20 is used as the input of the data latch 15, and the output of the adder 16 is used as the output of the digital filter.

Here, the adder 40 inputs the upper n'1 bits of one of the two inputs to the data latch 42, and the remaining lower n1-n>1 bits (nl).

n71 is an arbitrary integer (nx > nt) is used as one input of the adder 41a, and the remaining input is used as the adder 4.
1a, and the output of this adder 41a is used as the input of the data latch device 43, and the data latch device 42
．． The output of 43 is used as two inputs of adder 44, and adder 4
The output of the adder 40 is the output of the adder 40. Further, the coefficient unit 50 uses the upper n'2 bits of one of the two inputs as one input of the coefficient unit 51, and the remaining n3-02 bits are input to the coefficient unit 51.
Bit (nz, n'2 is an integer and nz > nz)
is one input of the coefficient multiplier 52, the other input is the remaining input of each of the coefficient multipliers 51.52, and the outputs of these coefficient multipliers 51.52 are respectively input to the data latch 5
3.54 inputs, and these data latches 53.54
The outputs of the adder 55 are the two inputs of the adder 55, and the output of the adder 55 is the output of the coefficient unit 50.

The delay time required for the calculation of the calculation loop consisting of the adder 40, the data latch 12, 14, and the coefficient unit 50 is 4 T s, and the coefficient of the coefficient unit 50 is (3/4'
) '=81/256.

Now adder 40, data latch 12, 14 and coefficient unit 5
The calculation loop consisting of 0 has a transfer characteristic of 1/(1-81/
It becomes an IIR filter with a transfer characteristic of 256.Z-4). Also, coefficient unit 18°24.29 and data latch unit 1
9, 21.23°25.26, 28.30.20 and adder 17°22.27 are 1+3/4・Z-'+9/1
6・Z-2+27/64 ・Z-3= 1 +n (3
/4) An FIR filter has a transfer characteristic of Z-1, and the data latch 15 and adder 16 form an FIR filter with a transfer characteristic of 1+Z-1. Therefore, as a whole, (1+Z-')・(1+3/4・Z-1+9/16・Z
-2+27/64 ・Z-')/(1-81/256・
If we configure a digital filter circuit with a transfer characteristic of Z-4) and simplify this transfer function, we get (1+Z-')/(1
-3/4・Z-1), which is the desired transfer characteristic.

In this case, the required speed for the coefficient unit 50 and the adder 40 is to perform one calculation each in a period of 2 T 1, and the digital filter circuit is can be configured.

For example, when processing a digital input that is sampled at four times the clock of the color subcarrier of an NTSC signal, in the first embodiment, the processing time of each of the coefficient multiplier and the adder is performed during a period of 70 ns. Good luck, second
In this embodiment, it is sufficient to execute the process within 140 ns.

〔Effect of the invention〕

As explained above, the present invention adds a second data latch to an arithmetic loop consisting of an adder, a first data latch, and a coefficient multiplier, and adjusts the coefficients by the delay time required for the operation of the arithmetic loop. By changing the coefficients of the filter and the transfer function of the FIR filter in relation to each other, it is possible to construct a circuit using relatively low-speed adders and coefficient units without using high-speed adders and high-speed coefficient units. effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the invention, and FIG. 3 is a block diagram of an example of a conventional digital filter circuit. 1... Digital input terminal group, 2... Output terminal group,
11.16.17,22,27,40,41°44.5
5...Adder, 12, 14, 15.19°20.21
,23,25,26.28.30°42.43,53.
54...Data latch device, 13°18.24,29,
50, 51.52...Coefficient unit.

Claims (1)

[Claims] a cyclic filter consisting of an arithmetic system having at least an adder, a first coefficient unit that multiplies a predetermined coefficient, and two or more data latch groups; and a cyclic filter that is connected in series with the cyclic filter and multiplies a coefficient of at least a real number k. A second coefficient unit and a data latch group are provided with an acyclic filter consisting of an arithmetic system having N stages (N is an integer of 1 or more), and the coefficient of the first coefficient unit is K^N. A digital filter circuit featuring: