JPH0795671B2 - Digital Filter - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter adapted to perform a filter process of a digital input signal with a circuit configuration having a small circuit scale.

〔Overview〕

According to the present invention, the same digit of a digital input signal delayed in a bit parallel manner in a batch manner using a shift register is used as an address signal, prestored operation data is read from a multiport memory, and each of the read data is read. By calculating the sum of the values obtained by multiplying the operation data by a constant, the circuit scale can be reduced and a circuit suitable for IC implementation can be configured.

[Conventional technology]

Generally, a digital filter is configured by using a multiplication circuit, a delay circuit, an addition circuit, etc. Among them, as a method of realizing the multiplication circuit, for example, the following is known.

(1) A serial multiplication system composed of a logical operation circuit and the like. This system is adopted in the fields of low-speed communication and voice processing, and has a small circuit scale, but it is not suitable for high-speed processing because partial products are added in a time-division manner.

(2) A parallel multiplication system configured by multiplication circuits provided in parallel.
This system is adopted in the field of digital audio and the like, and high-speed processing is possible, but the circuit scale is large.

(3) A method in which a bit shift circuit is used and only powers of 2 are multiplied. This method is used in the field of digital image processing and can be used when the filter specifications are fixed, but since it is a completely dedicated circuit and lacks versatility, mass production is possible and it is cost effective. It can only be used in circuits that can take advantage of.

(4) A memory multiplication method in which instead of a multiplier, the multiplication result is stored in a ROM or RAM as a table map, and a multiplier is used as an address signal to obtain a desired multiplication result from the table map. This method is often used for high-speed multiplication as well as the parallel multiplication method (2). When a ROM is used as the memory, the filter specifications are fixed, but the circuit configuration itself does not change even if the filter specifications are changed, which is different from the method (3). When RAM is used as the memory, the contents of the RAM can be rewritten at a low speed to change the filter specifications, so real-time processing is possible except when power is input or when filter characteristics are switched. Especially in the case of image processing, RA during blanking time
It is practical because M can be rewritten.

[Problems to be solved by the invention]

The memory multiplication method has a drawback in that, when the multiplication input word length is B, the required memory capacity is 2 ^B words per multiplication, and the memory capacity rapidly increases as the word length increases.

[Means for solving problems]

A digital filter according to the present invention comprises a shift register 1 for sequentially delaying a digital input signal AIN in a bit-parallel manner in a batch manner, and a bit of the same digit in a signal obtained by sequentially delaying a digital input signal using these shift registers 1. And an address generation circuit 3 for generating an address signal by extracting in a manner of bit slicing, and a filter calculation result calculated in advance is stored as calculation data, and the calculation data is duplicated corresponding to a plurality of input address signals. The multi-port memory 4 configured to be read out in a mode and the sum calculation circuit 5 that receives the operation data read from the multi-port memory 4 as an input and calculates the sum of the results of multiplying or bit-shifting the operation data by a predetermined constant. Composed.

[Action]

The digital input signal A _IN is input to the shift register 1 and sequentially delayed, and from the delayed signal, the address generation circuit 3 generates bits of the same digit, for example, MSB, 2ndMSB ...
The LSB is extracted in a bit-slicing manner to generate a plurality of address signals, the plurality of address signals are input to the multi-port memory 4, and the operation data stored in advance are read out. By inputting the read operation data to the sum calculation circuit 5 and outputting the result of performing the desired filter processing, the circuit scale can be reduced and the IC
Circuit configuration that is suitable for realization.

〔Example〕

 FIG. 1 shows the basic configuration of the present invention.

In FIG. 1, a shift register 1 is composed of registers R ₁ to R ₈ each having a B-bit parallel input / output terminal, and is used to add delay taps that are multiplied by symmetrical coefficients of a linear phase FIR digital filter. The B-bit input signal A _IN input to the register R ₁ is sequentially delayed so that it is output from the output terminals of the register R ₁ and the registers R ₂ to R ₈ connected thereto. For example, the B-bit parallel tap output signals sequentially delayed by one clock cycle are output.

These registers R ₁ to a digital signal each B-bit output from R _8, registers as shown R ₁ and R _8, R ₂
And R ₇ , R ₃ and R ₆ , and R ₄ and R ₅ output signals are input to adders 2-1 to 2-4 each having a B + 1 bit arithmetic capability to calculate the sum. As a result, the number of signals to be multiplied can be reduced by half.

The address generation circuit 3 is for extracting a plurality of address signals by extracting bits in the same digit of the addition outputs from the adders 2-1 to 2-4 in a manner of bit slicing.

The multiport memory 4 is configured such that a plurality of address signals are input and the filter operation results for each bit digit stored in advance as operation data in association with the address signals can be read in an independent manner. Of the adders 2-1 to 2-4 extracted by the address generation circuit 3 in the manner of bit-slicing the bit of the same digit in the memory having a plurality of address inputs and a plurality of output ports. Is entered as the address of.

The sum calculation circuit 5 receives the operation data read from the multi-port memory 4 as an input, calculates the sum of the results of multiplying or bit-shifting the operation data and obtaining a filter output.

This is based on the fact that the multiplication can be constructed by adding the partial products of the multiplier with the bitwise multiplicand. In a FIR (Finite Impulse Response) type digital filter, input data is guided to a delay circuit (for example, shift register 1), data of each tap of this delay circuit is multiplied by a filter coefficient, and all the multiplication results are added. The filter output is obtained by first calculating the partial products of the filter coefficients for each bit digit of the data output from each tap of the delay circuit, and then weighting all these partial products of the bit digits. Should be taken into consideration and added. At this time, of course, the order of addition is irrelevant. Therefore, even if the input word length and the number of taps are arbitrarily divided and the outputs are added, the same result can be obtained.

A more detailed embodiment of the present invention and its operation will be described with reference to FIG. The same elements as those in FIG. 1 are given the same numbers and their explanations are omitted.

In FIG. 2, the shift register 1 includes, for example, a shift register 1-1 composed of registers R ₁ to R ₄ each having a parallel input / output terminal of 9 bits and a shift register 1-2 composed of registers R ₅ to R _{8 in} parallel. Is located in
The input signal A _IN and the input signal B _IN are sequentially delayed to obtain an output signal A _OUT and an output signal B _OUT, and a 9-bit parallel tap output is obtained from the output terminals of the respective registers R ₁ to R _8. Is configured.

Therefore, when an input signal A _IN is supplied from the register R _1, the register R ₁ and this is connected a register R ₂
To R ₄ output 9-bit parallel tap output signals sequentially delayed by, for example, 1 clock cycle, and similarly output signal A _OUT output from register R ₄ is input signal.
By inputting to the register R ₅ as B _IN , a 9-bit parallel tap output signal sequentially delayed by, for example, one clock cycle is output from the register R ₅ and the registers R ₆ to R ₈ connected thereto. . The register
A switch is provided between R ₅ and R ₆ to switch between an even number and an odd number of taps. When using the shift register 1 alone, the number of taps can be switched from 8 to 7. You can

The 10-bit signal obtained by adding the 9-bit parallel tap output signals output from the registers R ₁ to R ₈ by the adders 2-1 to 2-4 is the flip-flop (FF) 3-1.
To 3-40 depending on the bit of the same digit, eg MSB, 2nd
MSB ... LSB is extracted in a bit sliced manner. This flip-flop (FF) 3-1 to 3-40
Although it is not always necessary, it is necessary when performing high-speed processing by pipeline processing.

The extracted signal is input to the multiport memories 4-1 and 4-2 as an address signal, and the filter operation result for each bit digit stored in advance as operation data in association with the address signal is independent. It is output in the form. The multi-port memories 4-1 and 4-2 are, for example, 16 words and 5 ports, respectively. Since the number of taps in shift register 1 is halved to 4
The memory capacity may be 2 ⁴ = 16 (word). Input word length is 9
Although it is a bit, it becomes 10 bits by addition, so 10
We have prepared for the port. In this embodiment, the word length is divided into two by providing two multiport memories. Although not shown, one input port is separately prepared for each of the multiport memories 4-1 and 4-2 in order to write a predetermined calculation result or the like. On the other hand, in the case of reading, each port can be read simultaneously from all ports, and even if the same address is input to each address terminal, the operation result corresponding to the address is independent of each other. It can be read from each port.

The sum calculation circuit 5 includes a register R, an adder, and a multiplier (“× 2”, “× 4”, etc.). This multiplier performs weighting for each bit digit based on the so-called bit-slicing principle when the address signals input to the multiport memories 4-1 and 4-2 are generated. It's an easy thing to do. The arithmetic data read from the multiport memory 4-1 is subtracted based on the address signal generated by extracting the MSB. This is because it is assumed that the circuit handles data in the 2's complement notation.

The adder 5-1 is for tap expansion, and is for vertically connecting the digital filters having the configuration shown in FIG. 2 to expand the number of taps. In this case, in order to expand the number of shift registers R _i (i is 1 to 8), a plurality of the same ones as shown in FIG. 2 may be prepared and vertically connected. That is, inputs the output signal A _OUT of one stage to the next stage of the input signal A _IN, and inputs an output signal B _OUT of the preceding stage to the input signal B _IN of a certain stage. In the shift register at the final stage, the switch SW is switched depending on whether it is an odd tap filter or an even tap filter. This switch is the shift register R ₅
And the shift register R ₆ are connected. In addition, the filter calculation output signal C _OUT is used as the next filter calculation input signal.
Input to C _IN . When expanded, the filter calculation input signal C _IN
Becomes an input signal from the outside, and the filter calculation output signal C
_OUT becomes an output signal to the outside.

Since the multi-port memory 4 is composed of RAM, the filter specifications can be easily changed by rewriting the stored contents. For example, when used to separate Y (luminance signal) and C (color signal) of TV, it is possible to easily change the filter specifications to desired contents by rewriting the contents during the blanking time. It is possible.

As described above, the bits of the same digit of each delayed input signal are extracted in a manner of bit-slicing to generate an address signal, and the generated address signal is generated by the multiport memories 4-1 and 4-. Since the desired calculation result is input to 2 and the desired calculation result is read out to perform the filter processing, it is possible to construct a digital filter having an extremely small circuit scale.

〔The invention's effect〕

As described above, according to the present invention, the shift register is used to generate the address signals of the bit-sliced mode at the same digit of the input signal delayed in parallel in a batch mode, and the generated address signals are generated. Since a filter calculation result for each bit digit stored in advance using the address signal is read, and a configuration is adopted in which the sum of the values obtained by multiplying each read calculation result by a constant is calculated,
It is possible to construct a digital filter having a small circuit scale and suitable for use as an IC. Further, by performing pipeline processing, it is possible to perform filter calculation processing at a higher speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a shift register, 2-1 to 2-4, 5-
1 is an adder, 3 is an address generation circuit, 4, 4-1 and 4-
Reference numeral 2 represents a multiport memory, and 5 represents a sum calculation circuit.

Claims (1)

[Claims] 1. A shift register for sequentially delaying digital input signals in a bit-parallel manner in a collective manner, and an adder for adding signals of the shift register having symmetrical coefficients among signals sequentially delayed by these shift registers. And an address generation circuit for simultaneously extracting a plurality of address signals for each same digit by extracting each bit of the same digit in each signal after being added by these adders in a mode of bit slicing, The multi-port memory configured to store the filter operation result as operation data and read the operation data in a duplicated manner in response to a plurality of input address signals, and the same digit for each digit from the multi-port memory. Of the above-mentioned operation data read simultaneously by a plurality of address signals of A digital filter comprising: a sum calculation circuit for calculating a sum of results obtained by multiplying or bit-shifting numbers, and configured to output an output result from the sum calculation circuit.